RELATED APPLICATIONS

[0001] This application claims benefit under 35 U.S.C. 119(e) of U.S. Provisional Application 63321935 filed March 21, 2023, the disclosure of which is incorporated herein by reference.

FIELD

[0002] Embodiments of the invention relate to interconnecting semiconductor dies.

BACKGROUND

[0003] Many optical and electronic circuits, such as hybrid and monolithic integrated circuits, comprise semiconductor dies that are connected by electrically conductive interconnects. Typically, the interconnects are bond wires that are attached to a metallization layer of a first die and to a metallization layer of a second die or a trace of a circuit board.

[0004] For example, a high voltage converter or power switch operated to deliver power to a device from a power source may comprise a normally OFF silicon MOSFET die having an array of normally OFF enhancement mode MOSFET transistors connected in series by a plurality of wire bonds to a normally ON lateral GaN die having an array of normally ON depletion mode transistors. To deliver suitably switched current to the device, the power switch may be rapidly turned ON and OFF to couple and decouple the power source to and from the device, and may be required to operate in a range of temperatures from an ambient temperature of about -55° C to a temperature as high as 175° C.

[0005] To provide efficient and reliable provision of power under the operating conditions the plurality of wire bonds and their respective bond joints at the dies are required to have as low an impedance as possible and to exhibit a satisfactory degree of resistance to damage, such as breakage and/or peeling, caused by mechanical stress generated by repeated heat cycling.

SUMMARY

[0006] An aspect of an embodiment of the disclosure relates to providing a physically robust interconnect, hereinafter also referred to as an “area interconnect”, that exhibits relatively low impedance and low coefficient of thermal expansion (CTE) for electrically connecting a semiconductor die comprised in an integrated circuit to another component of the integrated circuit. [0007] In an embodiment, an area interconnect comprises a monolithic contact conductor having a first contact region for electrically connecting the monolithic conductor to the semiconductor die, and a second contact region for electrically connecting the contact conductor and thereby the die to the other component of the circuit. The first contact region is, optionally planar, and patterned to overlay and to bond and electrically connect to a relatively large area of a metallization layer of the semiconductor die that is electrically connected to circuit elements of the die. Optionally, the first contact region is patterned to substantially congruently overlay the metallization layer. The second contact region is, optionally planar, and patterned to overlay and to bond and electrically connect to a relatively large area of a metallization layer of the other component of the circuit to which the die is intended to be connected. Optionally, the second contact region is patterned to substantially congruently overlay the metallization layer of the other component of the circuit. In an embodiment, the contact conductor has thickness that provides the first contact region with resistance substantially less than that of the metallization layer of the die. As a result, the first contact region cooperates with the metallization layer of the die to reduce inter alia the on-resistance of the die. The low CTE of the contact conductor contributes to maintaining integrity of the bonding of the contact region to the metallization layer and moderates strain that the contact region may generate in components of the die with change in operating temperature of the die.

[0008] In an embodiment the contact conductor of an area contact interconnect is formed from a low CTE metal such as by way of example, Molybdenum (Mo), Tungsten (W), or Laminate Copper- Invar-Copper (CIC). In an embodiment an area contact interconnect comprises a low CTE plate, such as a ceramic plate, and a contact conductor comprising a patterned layer of a conductive material, such as a metal, bonded to a face surface of the low CTE plate. Optionally, the patterned layer of the contact conductor is one of a pair of conductive layers that are bonded to opposite face surfaces of the low CTE plate that is sandwiched between the conductive layers. Optionally, the other conductive layer comprises a relatively large, optionally non-patterned, conductive layer covering a large portion of the face surface of the low CTE plate opposite to the face surface to which the contact conductor is bonded. Optionally, the conductive layers bonded to the face surfaces are formed from a relatively low resistivity, high CTE material such as copper (Cu) or Aluminium (Al).

[0009] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE FIGURES

[0010] Non-limiting examples of embodiments of the invention are described below with reference to figures attached hereto that are listed following this paragraph. Identical structures, elements or parts that appear in more than one figure are generally labeled with a same numeral in all the figures in which they appear. Dimensions of components and features shown in the figures are chosen for convenience and clarity of presentation and are not necessarily shown to scale.

[0011] Figs. 1A and IB schematically illustrate respective model configurations used to simulate and compare operation of a conventional die metallization and a conventional die metallization overlaid with a contact region of an area contact conductor, in accordance with an embodiment of the disclosure;

[0012] Figs 2A and 2B schematically respectively show a GaN die and the die attached to a substrate of a circuit in accordance with prior art;

[0013] Fig. 2C schematically shows conventional wire bond interconnects used to connect the GaN die with another die on the substrate, in accordance with prior art;

[0014] Figs. 2D-2F schematically show an area interconnect connecting the dies shown in Fig. 2B and 2C, in accordance with an embodiment of the disclosure; and

[0015] Figs. 3A-3D schematically show another area interconnect connecting the dies similar to those shown in Figs. 2B and 2C, in accordance with an embodiment of the disclosure.

DETAILED DESCRIPTION

[0016] In the discussion, unless otherwise stated, adjectives such as “substantially” and “about” modifying a condition or relationship characteristic of a feature or features of an embodiment of the disclosure, are understood to mean that the condition or characteristic is defined to within tolerances that are acceptable for operation of the embodiment in an application for which it is intended. Wherever a general term in the disclosure is illustrated by reference to an example instance or a list of example instances, the instance or instances referred to, are by way of nonlimiting example instances of the general term, and the general term is not intended to be limited to the specific example instance or instances referred to. The phrase “in an embodiment”, whether or not associated with a permissive, such as “may”, “optionally”, or “by way of example”, is used to introduce for consideration an example, but not necessarily required, configuration of possible embodiments of the disclosure. Each of the verbs, “comprise” “include” and “have”, and conjugates thereof, are used to indicate that the object or objects of the verb are not necessarily a complete listing of components, elements or parts of the subject or subjects of the verb. Unless otherwise indicated, the word “or” in the description and claims is considered to be the inclusive “or” rather than the exclusive or, and indicates at least one of, or any combination of more than one of items it conjoins.

[0017] Fig. 1A schematically shows a portion of a simulated normally ON, lateral GaN die 20 comprising a plurality of rows 22 of GaN transistors 24, each transistor having a source 25 and drain 26, in accordance with prior art. In the figure only four of the plurality of rows 22 of GaN transistors 24 in die 20 are shown.

[0018] Die 20 comprises first and second metallization layers 31 and 32, portions of which overlaying the portion of die 20 are schematically shown in Fig. 1A. First metallization layer 31, also referred to as source metallization layer 31, provides conductive connections to sources 25 of transistors 24 in die 20 and metallization layer 32, also referred to as drain metallization layer 32, provides conductive connections to drains 26 of the transistors. Filled and open circles 37 and 38 respectively represent connections, of the metallization layers to sources 25 and drains 26 which are made without the use of redistribution layers (RDEs).

[0019] Source metallization layer 31, comprises a plurality of tapered “source" fingers 33 extending from a common “source palm” 35. Each source finger 33 is electrically connected to each source 25 of GaN transistors 24 in two adjacent transistor rows 22. Drain metallization layer 32, comprises a plurality of tapered drain fingers 34 extending from a common drain palm 36. Each drain finger 34 is electrically connected to each drain 26 of GaN transistors 24 in two adjacent transistor rows 22. Source fingers 33 and drain fingers 34 are interleaved. When die 20 is turned ON, current from a power source (not shown) connected to the die flows from the power source to enter the die through source metallization layer 31, pass through transistors 24, and exit the die via drain metallization layer 32. In entering the die the current flows from palm 35 through fingers 33 of source metallization layer 31 to sources 25 of transistors 24 and then flows through current channels (not shown) of the transistors to transistor drains 26. In exiting the die the current flows from transistor drains 26 through fingers 34 to palm 36 of drain metallization layer 32.

[0020] A simulation experiment conducted to assess the electrical characteristics of the portion of die 20 shown in Fig. 1A assumed that source and metallization layers 31 and 32 were 4.5 pm (microns) thick and formed from Al having resistivity 2.6x 10"^ Qm (ohm-meters) and CTE equal to about 25.2 ppm/°C. The simulation indicated that the portion is expected to exhibit an on-resistance of about 130.6 mfi (milliohms). Assuming that the complete die 20 comprises 48 rows 22 of GaN transistors 24, die 20 is expected to be characterized by an on-resistance of aboutlO.88 mfi.

[0021] For most applications it is advantageous that semiconductor MOSFET dies, such as for example die 20, that operate as switches operate as closely as possible to ideal switches, and when turned ON to carry current, exhibit very little, advantageously substantially zero drainsource resistance (Rdson) to current flow through the semiconductor die. To determine potential advantages of an area interconnect and contact conductor in accordance with an embodiment of the invention on electrical characteristics and Rdson of a MOSFET die, a simulation experiment was carried out to determine their effect when applied to MOSFET die 20.

[0022] Fig. IB schematically shows the portion of die 20 shown in Fig. 1A as used in the simulation experiment having contact regions 102 and 112 of area interconnects (not shown) overlaying portions of metallization layers 31 and 32 (Fig. 1A), in accordance with an embodiment of the disclosure. Contact region 102 overlays and is bonded to electrically connect to source metallization layer 31 shown in Fig. 1A and may be referred to as source contact region 102. Source contact region 102 is optionally configured to, substantially congruently, overlay source metallization 31 (Fig. 1A) and comprises tapered source fingers 103 that extend from a source palm 104. Similarly, contact region 112 overlays and is bonded to electrically connect to drain metallization layer 32 shown in Fig. 1A and may be referred to as drain contact region 112. Drain contact region 112 is optionally configured to, substantially congruently, overlay drain metallization 32 and comprises tapered drain fingers 113 that extend from a drain palm 114. Source and drain fingers 103 and 113 are interleaved.

[0023] In the simulation experiment, the source and drain contact regions 102 and 112 were assumed to be 100 pm thick patterned layers of Molybdenum (Mo), which has resistivity of about 5.3x10’8 ohm-m and CTE equal to about 4.8 ppm/°C. For the assumed features of the Mo source and drain contact regions 102 and 112, and the thickness noted above assumed for Al metallization layers 31 and 32, resistances of the Mo contact regions are less than about 10% of the Al metallization layers over which the Mo contact regions lie. The simulated source and drain contact regions improved the simulated Rdson for die 20 by about 50% and reduced the Rdson from about 130 mfi to about 66 mfi. [0024] Fig. 2A schematically shows a complete optionally lateral n-channel GaN die 40 similar to GaN die 20 of which a portion is shown in Figs. 1A and IB. Gan die 40 comprises rows of GaN transistors (not shown) formed on a substrate 42 and source and drain metallization layers 55 and 51 that provide electrical contact to sources and drains of the GaN transistor formed in the die. Source metallization layer 55 has a source palm 56 from which source fingers 57 extend to lie over the GaN transistors for which the fingers make electrical contact with the transistor sources. Similarly drain metallization layer 51 has a drain palm 52 from which drain fingers 53 extend to lie over the GaN transistors for which the fingers make electrical contact with the transistor drains. Metallization layers 31 and 32 are assumed formed from a layer of 4.5 m Al.

[0025] Fig. 2B schematically shows a semiconductor circuit 60 comprising GaN die 40 and a vertical p-channel die 80 that are mounted to an optionally ceramic substrate 62 of the die in accordance with prior art. Die 80 is mounted to a metallization contact electrode 64 formed on substrate 62 that provides contact to circuit 60 and die 80 and is electrically connected to drains of transistors (not shown) comprised in the die. A metallization contact electrode 63 formed on substrate 62 provides contact to circuit 60 and is intended to be connected to drain metallization layer of die 40 to provide contact with die 40. Source metallization 55 of die 40 is to be connected to source metallization layer 81 of GaN die 40 to enable a desired operation of circuit 60.

[0026] As schematically shown in Fig. 2C, in accordance with prior art, electrical contact between source metallization layer 81 of die 80 and source metallization layer 55 of GaN die 55 is made by wire bonds 91. Bond wires 92 make electrical contact between drain metallization layer 51 of GaN die 40 and contact electrode 63.

[0027] Wire bonds 91 and 92 typically have CTEs between about 18-23 ppm/°C whereas the ceramic components of circuit 60 and components of dies 40 and 80 are characterized by relatively low CTEs that typically vary within a range of from about 2 ppm/°C to about 7 ppm/°C. As a result, the wire bonds are subject to breakage and peeling resulting from stress generated by thermal cycling. In addition, their shape typically increases stray inductance that contributes to, usually undesirable, impedance.

[0028] Fig. 2D schematically shows area interconnect contact conductors 100 and 110, portions of which are shown in Fig. IB, that may be used to respectively connect GaN die 40 to die 80 and the GaN die to metallization electrode 64 of circuit 60, in accordance with an embodiment of the disclosure. Contact conductor 100 comprises contact region 102 having source palm 104 and fingers 103 discussed with respect to Fig. 2B and a large area contact region 101 for connecting to metallization layer 81 of die 80. Contact conductor 110 comprises contact region 112 having drain palm 114 and drain fingers 113, also discussed with respect to Fig. 2B, and a large area contact region 111 for connecting to metallization contact electrode 63. As indicated in figure 2D contact conductors 100 and 110 are, optionally, the only components of their respective area interconnects, and may for convenience also be referred to as area interconnects.

[0029] Source and drain contact regions 104 and 114 of area interconnects 100 and 110 are optionally configured to lie substantially congruently on source metallization 55 and drain metallization 51 respectively when electrically attached to GaN die 40. Fig. 2E schematically shows circuit 60 below Fig. 2D in similar orientation to area interconnects 100 and 110 shown in Fig. 2D to illustrate the close match between contact regions 102 and 112 and source and metallization layers 55 and 51 and between contact regions 101 and 111 and metallization layer 81 of die 80 and contact electrode 64 respectively. Fig. 2F schematically shows area interconnects 100 and 110 coupled to circuit 60 to electrically connect die 80 to GaN 40 and GaN 40 to contact electrode 63. Area interconnects 100 and 100 may be connected to dies 40, 80, and/or contact electrode 63 using any of various advantageous technologies such as by way of example, soldering sintering and/or adhesive bonding.

[0030] Figs. 3A and 3B schematically show a bottom view and top perspective view respectively of another area interconnect 170 in accordance with an embodiment of the disclosure. By way of example, area interconnect 170 is configured to electrically connect die 80 to GaN die 40 and die 40 to contact electrode 63 of circuit 60 shown in Fig. 3C below Fig. 3B.

[0031] As schematically shown in Fig. 3A, area interconnect 170 comprises a planar, optionally ceramic substrate 171 characterized by a low CTE between about 5-6 ppm/°C having bottom and top face surfaces 172 and 173 respectively and patterned conductive layers 180 and 190 formed on the bottom face surface. Conductive layers 180 and 190 are optionally metal layers, formed optionally from copper (Cu) and may be referred to as metallization layers. Metallization layer 190 is patterned to make contact between source metallization layer 55 of GaN die 40 and metallization layer 81 of die 80. Metallization layer 190 comprises a contact region 191, which may be referred to as a palm 191, and a plurality of tapered fingers 192 that extend from the palm. Palm 191 is configured to overlay and contact, optionally substantially congruently, metallization layer 81. Fingers 192 are configured to overlay and contact, optionally substantially congruently, fingers 57 of metallization layer 55 of Gan die 40. Metallization layer 180 comprises a palm 181 and fingers 182 that are configured to overlay and contact, optionally substantially congruently, fingers 57 of metallization layer 51 of Gan die 40. Palm 181 is configured to make electrical contact with contact electrode 63 via contact spacers 66 formed on the contact electrode as schematically shown in Fig. 3C and discussed below.

[0032] In an embodiment, as schematically shown in Fig. 3B, a conductive layer 200 is formed on top face surface 173 of ceramic plate 171, optionally covering substantially all the area of the face surface. Optionally, conductive layer 200 is formed from a same material from which metallization layers 180 and 190 are formed. Conductive layer 200 and metallization layers 180 and 190 may be formed from a low CTE metal such as Mo but also from a metal have a relatively high CTE such as copper (Cu). By bonding conductive layer 200 and metallization layers 180 and 190 to low CTE substrate 171 the substrate operates to moderate thermal stress in in the high CTE metal. Having the conductive layer and metallization layers on opposite face surfaces of the ceramic substrate operates to moderate torque generated by the thermal stress that may bend the substrate and thereby area interconnect 170.

[0033] It is noted that due to thicknesses of die 80 and GaN die 40, metallization layer 81 of die 80 and metallization layers 51 and 55 GaN die 40 are raised with respect to the surface of substrate 62 to which the dies are bonded and to contact electrodes, such as contact electrode 63, formed on the substrate surface. On the other hand, metallization layers, such as metallization layers 180 and 190, formed on bottom surface 172 of area interconnect 170 are coplanar. To facilitate mounting of area interconnect 170 to circuit 60 and contact of metallization layers of the interconnect with contact electrodes formed on substrate 62, electrically conductive contact spacers 66 having top surfaces that are coplanar with metallization layers 81, 51, and 55 are mounted to the contact electrodes. For example, contact spacers 66 on contact electrode 63 have top surfaces that are coplanar with metallization layers 81, 51, and 55.

[0034] Fig. 3D schematically shows area interconnect 170 after mounting to circuit 60, to contact metallization layers 180 and 190 and contact spacers 66, in accordance with an embodiment of the disclosure.

[0035] Descriptions of embodiments of the invention in the present application are provided by way of example and are not intended to limit the scope of the invention. The described embodiments comprise different features, not all of which are required in all embodiments of the invention. Some embodiments utilize only some of the features or possible combinations of the features. Variations of embodiments of the invention that are described, and embodiments of the invention comprising different combinations of features noted in the described embodiments, will occur to persons of the art. The scope of the invention is limited only by the claims.