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Title:
SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2014/068814
Kind Code:
A1
Abstract:
The present invention reduces an operating voltage of a semiconductor light emitting device. This semiconductor light emitting device has, on a substrate, a first conductivity-type cladding layer formed of a III-V mixed crystal semiconductor, an active layer, and a second conductivity-type cladding layer. The second conductivity-type cladding layer is configured from a laminated structure having three or more layers, including a first layer, a second layer, and a third layer in this order from the active layer, the second layer and the third layer are included in a ridge formed by being processed into a stripe shape, the second layer is positioned at the skirt portion of the ridge, and the front surface of the first layer is a flat portion on both the sides of the ridge. When the Al compositions of the first layer, the second layer and the third layer are represented by X1, X2, and X3, respectively, the relationship of X2>X1, X3 is satisfied, and when the film thicknesses of the first layer, the second layer, and the third layer are represented by D1, D2, and D3, respectively, the relationship of D2

Inventors:
SATOH TOMOYA
YOKOYAMA TAKESHI
TAKASUKA SHOUICHI
KIDOGUCHI ISAO
Application Number:
PCT/JP2013/004258
Publication Date:
May 08, 2014
Filing Date:
July 10, 2013
Export Citation:
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Assignee:
PANASONIC CORP (JP)
International Classes:
H01S5/343; H01S5/22
Domestic Patent References:
WO2005124952A12005-12-29
WO2006077766A12006-07-27
Foreign References:
JPH05121829A1993-05-18
JP2004228340A2004-08-12
JPH1126864A1999-01-29
JPH11274657A1999-10-08
JPH03156989A1991-07-04
JP2002050831A2002-02-15
Attorney, Agent or Firm:
NAITO, Hiroki et al. (JP)
Hiroki Naito (JP)
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