Title:
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2023/106105
Kind Code:
A1
Abstract:
A semiconductor memory device (100) is provided with: a plurality of memory cells (112); a first power supply line (VDD); a second power supply line (VDDMC); a first transistor (T01) and a second transistor (T02) connected in parallel between the first power supply line (VDD) and the second power supply line (VDDMC); and a power supply control circuit (105) that, on the basis of a first signal (SDMC) for switching between a first mode (normal mode) in which a power supply voltage is supplied to the plurality of memory cells (112) and a second mode (power-down mode) in which the power supply voltage is not supplied to the plurality of memory cells (112), (i) turns off the first transistor (T01) and the second transistor (T02) during the second mode, and (ii) turns on the first transistor (T01) when switching from the second mode to the first mode and turns on the second transistor (T02) after turning on the first transistor (T01).
Inventors:
MOTOTANI ATSUSHI
Application Number:
PCT/JP2022/043303
Publication Date:
June 15, 2023
Filing Date:
November 24, 2022
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
G11C5/14; G11C11/417
Foreign References:
| US20080056048A1 | 2008-03-06 | |||
| JP2010198718A | 2010-09-09 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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