Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2009/069364
Kind Code:
A1
Abstract:
Provided is a highly integrated switching resistive RAM having an extremely
small occupation area of memory cells. Memory cells (11-14) are formed corresponding
to the four intersections of word lines (WL0, WL1) and bit lines (BL0, BL1). Each
of the memory cells (CEL11-CEL14) is composed of a switching layer (13) formed
on the surface of an N+ type Si layer (11). The switching layer (13) is electrically
connected to the corresponding bit lines (BL0, BL1) on the upper layer through
the electrode (14). The switching layer (13) is composed of a SiC layer (13A) laminated
on the surface of the N+ type Si layer (11), and a Si oxidation layer (13B)laminated
on the SiC layer (13A). The upper surface of the Si oxidation layer (13B) at the
top of the switching layer (13) is electrically connected to the corresponding
bit lines (BL0, BL1).
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Inventors:
SUDA YOSHIYUKI (JP)
OTA YUTAKA (JP)
OTA YUTAKA (JP)
Application Number:
PCT/JP2008/066499
Publication Date:
June 04, 2009
Filing Date:
September 08, 2008
Export Citation:
Assignee:
SANYO ELECTRIC CO (JP)
SANYO SEMICONDUCTOR CO LTD (JP)
UNIV TOKYO NAT UNIV CORP (JP)
SUDA YOSHIYUKI (JP)
OTA YUTAKA (JP)
SANYO SEMICONDUCTOR CO LTD (JP)
UNIV TOKYO NAT UNIV CORP (JP)
SUDA YOSHIYUKI (JP)
OTA YUTAKA (JP)
International Classes:
H01L27/10; G11C13/00; H01L45/00; H01L49/00
Foreign References:
JPH06275791A | 1994-09-30 | |||
JP2005538552A | 2005-12-15 | |||
JP2006313912A | 2006-11-16 |
Attorney, Agent or Firm:
SUTO, Katsuhiko (388 Komaigi-cho, Ota-sh, Gunma ., JP)
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