Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2012/005543
Kind Code:
A2
Abstract:
The present invention relates to a semiconductor memory device comprising a memory cell array and at least one sense amplifier, wherein the memory cell comprises at least one word line, at least one cell bit line, and at least one memory cell disposed on a region where the at least one word line and the at least one cell bit line cross each other, and the at least one sense amplifier is disposed on or under the memory cell array so as to flatly overlap the memory cell array, is connected to at least one bit line, which is connected to the at least one cell bit line, and to at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell. The at least one sense amplifier comprises a voltage reducing unit which reduces a voltage of a signal having a lower voltage level between signals of the at least one bit line and the at least one complementary bit line, a voltage boosting unit which boosts a voltage of a signal having a higher voltage level between the signals of the at least one bit line and the at least one complementary bit line, and an equalizing unit which equalizes the signals of the at least one bit line and the at least one complementary bit line.
Inventors:
YOON, Jae Man (1 Bongcheon Woosung Apt, 1706 Bongcheon-dong Gwanak-gu, Seoul 151-050, 151-050, KR)
Application Number:
KR2011/005022
Publication Date:
January 12, 2012
Filing Date:
July 08, 2011
Export Citation:
Assignee:
YOON, Jae Man (1 Bongcheon Woosung Apt, 1706 Bongcheon-dong Gwanak-gu, Seoul 151-050, 151-050, KR)
International Classes:
G11C7/06; G11C7/18
Attorney, Agent or Firm:
Y.P.LEE, MOCK & PARTNERS (1575-1, Seocho-dong Seocho-gu, Seoul 137-875, 137-875, KR)
Claims: