Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2012/098900
Kind Code:
A1
Abstract:
A semiconductor memory device is configured by memory cells that store and hold data and that are connected to word lines and bit lines, word line driver circuits connected to word lines, bit line precharge circuits connected to bit lines, and peripheral control circuits. First power sources (VDD) are connected to the memory cells and the peripheral control circuit, and to word line driver circuits (2) and bit line pre-charging circuits (3) via a switch element (MP1) controlled by a first control signal (PD). While area increase is kept small, leakage current during standby is effectively suppressed.
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Inventors:
YAMAGAMI YOSHINOBU
Application Number:
PCT/JP2012/000333
Publication Date:
July 26, 2012
Filing Date:
January 20, 2012
Export Citation:
Assignee:
PANASONIC CORP (JP)
YAMAGAMI YOSHINOBU
YAMAGAMI YOSHINOBU
International Classes:
G11C11/413; G11C11/41; G11C11/417
Foreign References:
JPH11219589A | 1999-08-10 | |||
JP2005032404A | 2005-02-03 | |||
JPH10261946A | 1998-09-29 | |||
JP2001015704A | 2001-01-19 | |||
JPH06203558A | 1994-07-22 | |||
JP2003132683A | 2003-05-09 | |||
JPS58211391A | 1983-12-08 |
Attorney, Agent or Firm:
NAITO, Hiroki et al. (JP)
Hiroki Naito (JP)
Hiroki Naito (JP)
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Claims: