Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/079863
Kind Code:
A1
Abstract:
[Problem] To more suitably perform a read-out operation. [Solution] This semiconductor memory device comprises: one or more first memory cells connected in parallel between a first voltage supply line that supplies a first voltage, and a second voltage supply line that supplies a second voltage different than the first voltage; and one or more second memory cells connected in parallel between the second voltage supply line and a third voltage supply line that supplies the first voltage. Each of the first memory cells has a first memory element having a resistance value corresponding to a first state or a second state, and a first cell transistor connected between the first memory element and the first voltage supply line. Each of the second memory cells includes: a second memory element having a resistance value corresponding to a first state or a second state; and a second cell transistor connected between the second memory element and the third voltage supply line.
Inventors:
NARITAKE ISAO (JP)
ISHIKAWA NOBUYUKI (JP)
KINOSHITA YOSHIHIKO (JP)
MOTOMURA TETSUO (JP)
IKEDA KAZUFUMI (JP)
OJIRO TSUKASA (JP)
SHIMADA TOMOKO (JP)
NAGAMATSU KENICHI (JP)
WATANABE KOJI (JP)
ISHIKAWA NOBUYUKI (JP)
KINOSHITA YOSHIHIKO (JP)
MOTOMURA TETSUO (JP)
IKEDA KAZUFUMI (JP)
OJIRO TSUKASA (JP)
SHIMADA TOMOKO (JP)
NAGAMATSU KENICHI (JP)
WATANABE KOJI (JP)
Application Number:
PCT/JP2022/036022
Publication Date:
May 11, 2023
Filing Date:
September 27, 2022
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G11C7/14; G11C17/16; G11C17/18
Foreign References:
| JP2013251035A | 2013-12-12 | |||
| JP2017142869A | 2017-08-17 |
Attorney, Agent or Firm:
MIYAJIMA Manabu (JP)
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