SEMICONDUCTOR MEMORY DEVICE

WIPO Patent Application WO/2023/195047

A1

This semiconductor memory device comprises: a p layer 1 that is a semiconductor matrix; an n+ layer 2 that extends to one side; a second impurity layer n+ layer 3 that is in contact with the p layer 1 on the opposite side to the n+ layer 2; a first gate conductor layer 5 that covers a portion of the p layer 1 with a first gate insulating layer 4 and is in contact with the first gate insulating layer 4; and a second gate conductor layer 7 that is in contact with the gate insulating layer 4 and covers a portion of the p layer 1 with a second gate insulating layer 6 while being electrically isolated from the gate electrode 5, wherein voltages are applied to the n+ layer 2, the n+ layer 3, and the gate conductor layers 5 and 7 to perform memory operations. The semiconductor memory device is characterized in that a value obtained by dividing the impurity concentration of a region 1b by the gate capacitance of a MOS structure, which is formed by the gate conductor layer 7, the gate insulating layer 6, and the p layer 1, per unit area is larger than a value obtained by dividing the impurity concentration of a region 1a by the gate capacitance of a MOS structure, which is formed by the gate conductor layer 5, the gate insulating layer 4, and the p layer 1, per unit area at the time of the memory operations.

KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)

PCT/JP2022/017049

October 12, 2023

April 04, 2022

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UNISANTIS ELECT SINGAPORE PTE (SG)
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)

H01L21/336; H01L27/105; H01L29/788; H01L29/792

US20200135863A1	2020-04-30
JP2009252264A	2009-10-29
JP2003188279A	2003-07-04
JP2008147514A	2008-06-26

TANAKA Shinichiro et al. (JP)

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