Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/204111
Kind Code:
A1
Abstract:
A plurality of SRAM cells (C1) are commonly connected to both a write bitline (WBL, WBLB) extending in a Y-direction and a local read bitline (RBL) extending in the Y-direction. A local amplifier (B1) connected to the local read bitline (RBL) outputs, to a global read bitline (GRBL), a signal received from a selected SRAM cell (C1) via the local read bitline (RBL). A buried wire (11) corresponding to the global read bitline (GRBL) is formed in a buried wiring layer. A wire (706) corresponding to the local read bitline (RBL) is formed in a first wiring layer.
Inventors:
HIROSE MASANOBU (JP)
Application Number:
PCT/JP2023/014770
Publication Date:
October 26, 2023
Filing Date:
April 11, 2023
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H10B10/00; G11C7/18; G11C11/412; H01L21/8238; H01L27/092
Domestic Patent References:
| WO2021125094A1 | 2021-06-24 | |||
| WO2021166645A1 | 2021-08-26 |
Foreign References:
| US20150041885A1 | 2015-02-12 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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