Title:
SEMICONDUCTOR MEMORY UNIT
Document Type and Number:
WIPO Patent Application WO/2011/145274
Kind Code:
A1
Abstract:
A transistor (TP0) comprises a source connected to a power source node, a drain connected to a local bit line (104), and a gate connected to a write global bit line (107). A transistor (TP1) comprises a source connected to a power source node, a drain connected to a local bit line (105), and a gate connected to a write global bit line (106). A transistor (TN0) comprises a source connected to the write global bit line (106), a drain connected to the local bit line (104), and a gate to which a control signal (PASS<0>) is provided. A transistor (TN1) comprises a source connected to the write global bit line (107), a drain connected to the local bit line (105), and a gate to which the control signal (PASS<0>) is provided. A readout circuit (112) is connected to the local bit lines (104, 105) and to readout global bit lines (108, 109).
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Inventors:
KOIKE, Tsuyoshi (())
小池剛 (())
小池剛 (())
Application Number:
JP2011/002388
Publication Date:
November 24, 2011
Filing Date:
April 22, 2011
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
KOIKE, Tsuyoshi (())
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
KOIKE, Tsuyoshi (())
International Classes:
G11C11/419; G11C11/401; G11C11/4096; G11C11/41; G11C11/417
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
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Claims:
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