SEMICONDUCTOR MEMORY

WIPO Patent Application WO/2004/088667

A1

A delay trigger signal is generated by delaying any one of timing signals being generated in response to a command signal received in synchronism with a clock signal. A clock trigger signal is generated in synchronism with the transition edge of a clock signal after receiving the command signal. The delay trigger signal or the clock trigger signal is selected depending on the frequency of the clock signal and the transition edge of a core control signal for operating a core memory is generated in synchronism with the selected signal. Consequently, the core control signal can be generated constantly at an optimal timing even when the frequency of the clock signal is varied. Timing margin of the core control signal can thereby be enhanced and the yield can be increased. Since the timing margin is enhanced, timing design is facilitated and the cost required for developing a semiconductor memory can be reduced.

YAGISHITA YOSHIMASA (JP)

PCT/JP2003/004071

October 14, 2004

March 31, 2003

Click for automatic bibliography generation  

FUJITSU LTD (JP)
YAGISHITA YOSHIMASA (JP)

G11C7/10; G11C7/22; G11C11/4076; (IPC1-7): G11C11/407

JP2000011663A	2000-01-14
JP2000137998A	2000-05-16
JP2000215663A	2000-08-04
JPH11176161A	1999-07-02
JPH09139076A	1997-05-27
JP2001126480A	2001-05-11
JP2001344973A	2001-12-14
JP2001035195A	2001-02-09
JPH10162576A	1998-06-19
JP2002358784A	2002-12-13
JP2000021164A	2000-01-21
JPH11288589A	1999-10-19
JP2001210077A	2001-08-03
JP2000235790A	2000-08-29
JPH1069769A	1998-03-10
JPH1069770A	1998-03-10

Furuya, Fumio (9th Floor 19-5, Nishishinjuku 1-chom, Shinjuku-ku Tokyo, JP)

View/Download PDF      PDF Help

Previous Patent: MEDIA IDENTIFICATION

Next Patent: DEVICE AND METHOD FOR DETERMINING AN ELECTRICAL PROPERTY OF A SAMPLE