Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
WIPO Patent Application WO/2010/084539
Kind Code:
A1
Abstract:
Random variation from both memory cells (200) and peripheral circuits (201) will cause performance to deteriorate, and when combining constituent parts that have performance close to worst case ones, performance failure will occur on the macro level. As a counter measure, selectors (203) are interposed and switch the positive and negative phases of the bit lines. Alternatively, the bit line and sense amplifier combinations are switched between neighboring data input/output units or other measures are taken. That is, a remedy for performance failures is implemented so as to eliminate worst case combinations.
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Inventors:
ISHIKURA, Satoshi (())
石倉聡 (())
SUMITANI, Norihiko (())
石倉聡 (())
SUMITANI, Norihiko (())
Application Number:
JP2009/005712
Publication Date:
July 29, 2010
Filing Date:
October 28, 2009
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
ISHIKURA, Satoshi (())
石倉聡 (())
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
ISHIKURA, Satoshi (())
石倉聡 (())
International Classes:
G11C29/04; G11C11/413
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
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