Title:
SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2019/176912
Kind Code:
A1
Abstract:
This semiconductor module comprises: a sub-mount provided with an upper surface, a back surface, and side surfaces connecting the upper surface and the back surface; a semiconductor element solder-joined onto the upper surface of the sub-mount; and a block solder-joined onto the back surface of the sub-mount. The semiconductor element protrudes outward beyond a first side surface of the sub-mount. A recess is formed in each of a second side surface and a third side surface which are orthogonal to the first side surface of the sub-mount, the recesses extending in a direction from the upper surface to the back surface of the sub-mount. The recesses are arranged such that, in a state in which the upper surface of the sub-mount is suction-attached to a collet, protrusions of the collet are fixed in the recesses.
Inventors:
YONEDA YUTAKA (JP)
FUJINO JUNJI (JP)
HATA TADAYOSHI (JP)
SATO JIN (JP)
FUJINO JUNJI (JP)
HATA TADAYOSHI (JP)
SATO JIN (JP)
Application Number:
PCT/JP2019/009904
Publication Date:
September 19, 2019
Filing Date:
March 12, 2019
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H01S5/022; H01S5/0239
Foreign References:
JP2001217498A | 2001-08-10 | |||
JP2012033582A | 2012-02-16 | |||
JPH11233697A | 1999-08-27 | |||
JP2017059620A | 2017-03-23 | |||
JPH05218109A | 1993-08-27 | |||
JPH04315486A | 1992-11-06 | |||
US20060171434A1 | 2006-08-03 |
Attorney, Agent or Firm:
YAMAO, Norihito et al. (JP)
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