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Title:
SEMICONDUCTOR MODULE
Document Type and Number:
WIPO Patent Application WO/2019/202687
Kind Code:
A1
Abstract:
Semiconductor elements (4a to 4d) and a wiring element (5) are arranged on a major surface of a base plate (1). First wires (11a to 11e) connect external electrodes (7a to 7e) and first relay pads (8a to 8e) of the wiring element (5). Second wires (12a to 12e) connect pads (13a to 13e) of the semiconductor elements (4a to 4d) and second relay pads (9a to 9e) of the wiring element (5). A resin (15) seals the semiconductor elements (4a to 4d), the wiring element (5), and the first and second wires (11a to 11e, 12a to 12e). The second wires (12a to 12e) are thinner than the first wires (11a to 11e). The pads (13a to 13e) are smaller than the first relay pads (8a to 8e).

Inventors:
NAKATA YOSUKE (JP)
Application Number:
PCT/JP2018/016022
Publication Date:
October 24, 2019
Filing Date:
April 18, 2018
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H01L25/07; H01L21/60; H01L23/28; H01L23/52; H01L25/18
Domestic Patent References:
WO2012144070A12012-10-26
WO2017037942A12017-03-09
WO2010084550A12010-07-29
WO2014006724A12014-01-09
Foreign References:
JP2001284395A2001-10-12
JP2016162913A2016-09-05
JP2003204009A2003-07-18
JP2017022301A2017-01-26
JP2008211237A2008-09-11
Attorney, Agent or Firm:
TAKADA, Mamoru et al. (JP)
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