Title:
SEMICONDUCTOR-MOUNTED PRODUCT
Document Type and Number:
WIPO Patent Application WO/2018/134860
Kind Code:
A1
Abstract:
This semiconductor-mounted product comprises a semiconductor package, a wiring board, four or more solder joints, and resin-reinforcement parts. Each of the solder joints electrically connects the semiconductor package to the wiring on the wiring board. The resin-reinforcement parts are formed on the side surface of each solder joint. Each of the solder joints has a first solder region formed closer to the semiconductor package than to the wiring board, and a second solder region formed closer to the wiring board than to the semiconductor package. Within a polygon formed by joining, from among the solder joints, the centers of the solder joints positioned in the outermost section, the proportion of the voids relative to the sum of the voids and the resin-reinforcement parts is between 10% and 99% inclusive. The proportion of the voids is evaluated in a plane that is parallel to the mounting surface and separated from the mounting surface of the wiring board by only 1/4 of the distance between the semiconductor package and the wiring board.
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Inventors:
YAMAGUCHI ATSUSHI
FUKUHARA YASUO
FUKUHARA YASUO
Application Number:
PCT/JP2017/001307
Publication Date:
July 26, 2018
Filing Date:
January 17, 2017
Export Citation:
Assignee:
PANASONIC IP MAN CO LTD (JP)
International Classes:
H01L23/12; H01L21/60; H05K1/18
Domestic Patent References:
| WO2016017076A1 | 2016-02-04 |
Foreign References:
| JP2001085823A | 2001-03-30 | |||
| JP2014057008A | 2014-03-27 | |||
| JP2013062324A | 2013-04-04 |
Attorney, Agent or Firm:
KAMATA Kenji et al. (JP)
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