Title:
SEMICONDUCTOR PACKAGE HAVING REDUCED INTERNAL POWER PAD PITCH
Document Type and Number:
WIPO Patent Application WO/2019/096093
Kind Code:
A1
Abstract:
A packaged Integrated Circuit (IC) includes an IC and a package. The package has a bottom dielectric layer and a plurality of redistribution layers (RDLs) formed on the bottom dielectric layer. Each the RDLs includes patterned conductors, a dielectric layer, and a plurality of vias that extend between the patterned conductors to a differing RDL or to external connections. The package includes a plurality of package pads that have a first lateral separation pitch. The IC includes a plurality of IC pads that electrically connect to the plurality of package pads that have a first lateral separation pitch. The package also includes a plurality of Printed Circuit Board (PCB) pads that extend through the bottom dielectric layer and contact the plurality of patterned conductors of the first RDL. Power PCB pads and ground PCB pads of the plurality of PCB pads have a second lateral separation pitch that exceeds the first lateral separation pitch.
Inventors:
GU SHIQUN (US)
ZHANG HONGYING (CN)
CAI HONGLIANG (CN)
ZHANG HONGYING (CN)
CAI HONGLIANG (CN)
Application Number:
PCT/CN2018/115051
Publication Date:
May 23, 2019
Filing Date:
November 12, 2018
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H01L23/538; H01L23/31
Foreign References:
| CN106653703A | 2017-05-10 | |||
| CN106098665A | 2016-11-09 | |||
| CN104795382A | 2015-07-22 | |||
| CN101005058A | 2007-07-25 |
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