Title:
SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE INTERMEDIATE BODY, REWIRING LAYER CHIP, REWIRING LAYER CHIP INTERMEDIATE BODY, SEMICONDUCTOR PACKAGE MANUFACTURING METHOD, AND SEMICONDUCTOR PACKAGE INTERMEDIATE BODY MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2023/157892
Kind Code:
A1
Abstract:
This semiconductor package comprises: an interposer; a rewiring layer chip adjacent to the interposer; and a semiconductor element layered on the interposer and the rewiring layer chip. The rewiring layer chip includes: a rewiring element having a surface on which the semiconductor element is layered; and a first mold resin layer that contains a resin and that is attached to a surface of the rewiring element at a position on the side opposite the surface on which the semiconductor element is layered. The rewiring element has an insulation layer with insulating properties, and a first rewiring layer that is covered by the insulation layer. The first rewiring layer has a first conductive part, at least a portion of which is positioned on the surface of the rewiring element on which the semiconductor element is layered. The interposer has a second rewiring layer including a second conductive part positioned on the surface of the interposer on which the semiconductor element is layered. The semiconductor element is electrically connected to the first conductive part and the second conductive part.
Inventors:
KURAMOCHI SATORU (JP)
Application Number:
PCT/JP2023/005328
Publication Date:
August 24, 2023
Filing Date:
February 15, 2023
Export Citation:
Assignee:
DAINIPPON PRINTING CO LTD (JP)
International Classes:
H01L25/18; H01L23/12; H01L23/32; H01L25/065; H01L25/07; H05K3/46
Foreign References:
| JP2018093162A | 2018-06-14 | |||
| JP2020150192A | 2020-09-17 | |||
| JP2005039217A | 2005-02-10 | |||
| US20200128669A1 | 2020-04-23 |
Attorney, Agent or Firm:
MIYAJIMA Manabu et al. (JP)
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