CROSS-REFERENCE TO RELATED APPLICATION

[001] This application claims the benefit of priority of Singapore application No. 10201605613S filed on July 08, 2016, the contents of it being hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

[002] Various aspects of this disclosure relate to a semiconductor package. Various aspects of this disclosure relate to methods of forming a semiconductor package.

BACKGROUND

[003] Portable computing systems have become one of the major drivers in semiconductor industry. Such electronic systems include basically high performance logic, such as central processing unit (CPU) and graphic processing unit (GPU), and single or multiple memory modules, and carry out massive amount of data processing and transfers between CPU/GPU and memories. Therefore, significant storage capacity in memories and as well as higher data transfer capabilities (bandwidth) between logic and memory is required in order to meet the system demands.

[004] In order to serve that demand, high capacity memories are being introduced to the market while the IO density and per IO pin data-rates in new memory technologies are also being increased. Thus, the device IO pitch has gone down to 40 micrometer range, but the packaging technology is not improving at the same rate to support high IO count devices to be attached on them, because the current organic package technology allows a pitch of the order of 150 micrometer. In response to this gap between die and package IO mismatch, there are several interposer technologies and other package assemblies proposed by the industry. But they are relatively expensive, less reliable and complicated in semiconductor testing and handling during the process assembly stages. [005] High-Bandwidth Memory (HBM) introduced recently to the market to achieve next generation portable computing systems solves two key problems related to contemporary DRAM: it increases the bandwidth (BW) and reduces the power consumption. HBM (Genl) contains 3982 micro-bumps with a staggered pitch of 27.5 micrometer and 48 micrometer and the bump size is 25micrometer. The die-to-die input-output (IO) contacts in HBM (~1200) are located towards one edge so that the logic to memory channel length is reduced. However, in order to escape all these IOs and route them to CPU/GPU die, existing silicon interposer based packaging technologies can be used but they are prohibitively expensive due to foundry based multi-layer fine-pitch interconnects and large interposer size.

[006] Due to increasing performance demands in future computing platforms, the memory technology will go beyond HBM specifications and the die-to-die IOs is tend to increase in the future. Therefore, industry is after novel packaging technologies which will reduce the system cost and footprint in par with the performance improvements.

SUMMARY

[007] Various embodiments may provide a semiconductor package including:

a routing layer including one or more dielectric materials;

a plurality of first electrical routing layer contact elements and a plurality of second electrical routing layer contact elements on a first side of the routing layer;

a plurality of third electrical routing layer contact elements on a second side of the routing layer opposite the first side;

a first semiconductor die having a first side facing the first side of the routing layer, and a second side opposite the first side of the first semiconductor die; a plurality of first electrical die contact elements on the first side of the first semiconductor die; a plurality of second electrical die contact elements on the first side of the first semiconductor die; a second semiconductor die having a first side facing the first side of the routing layer, and a second side opposite the first side of the second semiconductor die; a plurality of third electrical die contact elements on the first side of the second semiconductor die;

a plurality of fourth electrical die contact elements on the first side of the second semiconductor die;

an interconnection die having a first side, and a second side opposite the first side; wherein a first portion of the first side faces at least a portion of the first side of the first semiconductor die and a second portion of the first side faces at least a portion of the first side of the second semiconductor die; and wherein the second side faces the first side of the routing layer;

a plurality of fifth electrical die contact elements on the first portion of the first side of the interconnection die;

a plurality of sixth electrical die contact elements on the second portion of the first side of the interconnection die;

a resin encapsulation structure covering at least a portion of the first semiconductor die, at least a portion of the second semiconductor die, and at least a portion of the interconnection die; one or more first resin encapsulated electrical interconnections extending vertically between the plurality of first electrical routing layer contact elements and the plurality of first electrical die contact elements to electrically connect the routing layer and the first semiconductor die; one or more second resin encapsulated electrical interconnections extending vertically between the plurality of second electrical routing layer contact elements and the plurality of third electrical die contact elements to electrically connect the routing layer and the second semiconductor die;

one or more third resin encapsulated electrical interconnections extending vertically between the plurality of second electrical die contact elements and the plurality of fifth electrical die contact elements to electrically connect the interconnection die and the first semiconductor die; and one or more fourth resin encapsulated electrical interconnections extending vertically between the plurality of fourth electrical die contact elements and the plurality of sixth electrical die contact elements to electrically connect the interconnection die and the second semiconductor die; wherein the routing layer includes one or more electrically conductive routing layer interconnections electrically coupling one or more of the plurality of third electrical routing layer contact elements with the first electrical routing layer contact elements contact elements, and one or more of the plurality of third electrical routing layer contact elements with the second electrical routing layer contact elements; and

wherein the interconnection die includes one or more electrically conductive interconnection die interconnections electrically connecting the plurality of fifth electrical die eontact elements and the plurality of sixth electrical die contact elements.

[008] Various embodiments may provide a method of forming the semiconductor structure, the method including:

providing a first semiconductor die having a first side and a second side opposite the first side of the first semiconductor die; a plurality of first electrical die contact elements on the first side of the first semiconductor die; and a plurality of second electrical die contact elements on the first side of the first semiconductor die;

providing a second semiconductor die having a first side and a second side opposite the first side of the second semiconductor die; a plurality of third electrical die contact elements on the first side of the second semiconductor die; and a plurality of fourth electrical die contact elements on the first side of the second semiconductor die;

providing an interconnection die having a first side, and a second side opposite the first side; and wherein the interconnection die further includes a plurality of fifth electrical die contact elements on the first portion of the first side of the interconnection die; and a plurality of sixth electrical die contact elements on the second portion of the first side of the interconnection die; wherein the interconnection die includes one or more electrically conductive interconnection die interconnections electrically connecting the plurality of fifth electrical die contact elements and the plurality of sixth electrical die contact elements; wherein a first portion of the first side of the interconnection die faces at least a portion of the first side of the first semiconductor die and a second portion of the first side of the interconnection die faces at least a portion of the first side of the second semiconductor die; forming one or more first resin encapsulated electrical interconnections extending from the plurality of first electrical routing layer contact elements; forming one or more second resin encapsulated electrical interconnections extending from the plurality of second electrical routing layer contact elements

forming one or more third resin encapsulated electrical interconnections extending vertically between the plurality of second electrical die contact elements and the plurality of fifth electrical die contact elements to electrically connect the interconnection die and the first semiconductor die; and

forming one or more fourth resin encapsulated electrical interconnections extending vertically between the plurality of fourth electrical die contact elements and the plurality of sixth electrical die contact elements to electrically connect the interconnection die and the second semiconductor die;

forming a resin encapsulation structure covering at least a portion of the first semiconductor die, at least a portion of the second semiconductor die, and at least a portion of the interconnection die;

forming a routing layer including one or more dielectric materials; and

forming a plurality of first electrical routing layer contact elements and a plurality of second electrical routing layer contact elements on a first side of the routing layer; and a plurality of third electrical routing layer contact elements on a second side of the routing layer opposite the first side;

the routing layer is formed so that the first side of the routing layer faces the first side of the first semiconductor die and so that the first side of the routing layer the first side of the second semiconductor die and further so that the first side of the routing layer faces the second side of the interconnection die; wherein the routing layer is formed so to be arranged in relation to the plurality of first electrical die contact elements to electrically connect the routing layer and the first semiconductor die, and in relation to the plurality of third electrical die contact elements to electrically connect the routing layer and the second semiconductor die; wherein the routing layer includes one or more electrically conductive routing layer interconnections electrically coupling one or more of the plurality of third electrical routing layer contact elements with the first electrical routing layer contact elements, and one or more of the plurality of third electrical routing layer contact elements with the second electrical routing layer contact elements. BRIEF DESCRIPTION OF THE DRAWINGS

[009] The invention will be better understood with reference to the detailed description when considered in conjunction with the non-limiting examples and the accompanying drawings, in which:

FIG. 1 shows schematic illustration of a semiconductor package 01 according to various embodiments, in the "inverted" position wherein the first semiconductor die 20 and the second semiconductor die 30 are above the routing layer 10.

FIG. 2 shows schematic illustration of the semiconductor package 01 according to figure 1 attached to a PCB 03.

FIG. 3 shows schematic illustration of another semiconductor package 01 according to various embodiments, wherein in addition to the first semiconductor die and the second semiconductor die a third and a fourth semiconductor dies comprised in the same semiconductor package. Also a second interconnection die is comprised.

FIG. 4 is a flow diagram of forming a semiconductor packaging according to various embodiments.

FIG. 5A and 5B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments. Fig. 5B is the continuation of Fig. 5 A.

FIG. 6A and 6B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments, wherein first and second resin encapsulated electrical interconnections 51 and 52 are fabricated after die mounting of the first semiconductor die 20 and the second semiconductor die 30 on a carrier 70. Fig. 6B is the continuation of Fig. 6A.

FIG. 7A and 7B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments, wherein part, e.g. the substrate 49, of the interconnection die 40 is etched away enabling connection paths on the second side 42 of the interconnection die 40. Fig. 7B is the continuation of Fig. 7A.

FIG. 8 is a schematic repeated from Fig. 7B step 7.g to show the plane 61, first plane 63, and second plane 64. The lines indicating the planes are not shown in the other figures to improve visibility. DETAILED DESCRIPTION

[010] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[011] Embodiments described in the context of one of the methods or memory cells/devices are analogously valid for the other methods or memory cells/devices. Similarly, embodiments described in the context of a method are analogously valid for a memory cell/device, and vice versa.

[012] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[013] The word "over" used with regards to a deposited material formed "over" a side or surface, may be used herein to mean that the deposited material may be formed "directly on", e.g. in direct contact with, the implied side or surface. The word "over" used with regards to a deposited material formed "over" a side or surface, may also be used herein to mean that the deposited material may be formed "indirectly on" the implied side or surface with one or more additional layers being arranged between the implied side or surface and the deposited material. In other words, a first layer "over" a second layer may refer to the first layer directly on the second layer, or that the first layer and the second layer are separated by one or more intervening layers.

[014] The word "inverted" or "flipped" is used with regards to the orientation of a semiconductor die. Conventionally a semiconductor die is non-inverted or non-flipped if the substrate, or carrier, is facing downwards. The largest carrier is usually drawn at the bottom, because that also corresponds to the usual position in a manufacturing process. [015] The device arrangement as described herein may be operable in various orientations, and thus it should be understood that the terms "top", "bottom", etc., when used in the following description are used for convenience and to aid understanding of relative positions or directions, and not intended to limit the orientation of the device arrangement.

[016] In the context of various embodiments, the articles "a", "an" and "the" as used with regard to a feature or element include a reference to one or more of the features or elements.

[017] In the context of various embodiments, the term "about" or "approximately" as applied to a numeric value encompasses the exact value and a reasonable variance.

[018] As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

[019] Use of the plural, for example "elements" as in electrical die contact elements, "interconnections" as in resin encapsulated electrical interconnections, refers that there is a plurality. When referring to a connection of such elements, it means that one or more, e.g. a plurality, is being connected, also written as coupled. The skilled in the art will understand that for semiconductor connections, the suitable connection will be chosen according to the envisaged application, so that not necessarily all of a plurality of "elements" or "interconnections" need to be connected. For example, the "routing layer includes electrically conductive routing layer interconnections electrically coupling the third electrical routing layer contact elements with the first electrical routing layer contact elements " means "the routing layer includes one or more electrically conductive routing layer interconnections electrically coupling one or more of the plurality of third electrical routing layer contact elements with one or more of the first electrical routing layer contact elements". Obviously it is not necessary that all of the plurality are connected. The skilled in the art will understand that it means that those contact elements that provide the desired electronic function are connected. There could be other contact elements that are not required for a desired function, that are left unconnected.

[020] The terms "grinding" or "back grinding" have the common meaning in the technical field of semiconductors.

[021] The figures are of schematic nature, the proportion and the number of connections is modified to improve the visibility and to easier explain the invention. When there is a reference to a plurality of elements, these may in reality be of a different number as shown in the figure, e.g. of a larger number. The figures are mainly schematic illustrations of cross- sections, wherein some connections are shown in two dimensions as exemplary only.

[022] The used reference numerals are the same across the figures, and are grouped in a consistent way as can be seen in the reference list at the end of the specification, to facilitate the understanding of the figures.

[023] According to the invention, the contact elements, e.g. as shown in the figures, elements 23, 33, 24, 43, 34, 44, are e.g. metallized. The figures show the respective contact elements of the dies being flush with the die surface, however it the contact elements can also be provided non-flush, thus at least partially out of the surface plane of the respective die. It is preferred that the contact elements inelude under bump metallization (UBM).

[024] Various embodiments provide novel packaging technologies which may reduce the system cost and footprint in par with the performance improvements. The presently proposed fan-out packaging technology uses fewer thick metallization layers with an embedded fine pitch interconnect (EFI) die and wafer level assembly process. There is also proposed a process for producing such package.

[025] The present invention allows for increased bandwidth of high-speed electronic systems with novel techniques to meet fine-pitch IO requirements. The invention also provides a greater flexibility for signal and power/IO routing.

[026] Figure 1 shows a semiconductor package 01 according to various embodiments. The semiconductor package 01 includes a routing layer 10 including one or more dielectric materials 02, a first semiconductor die 20, a second semiconductor die 30, and an interconnection die 40.

[027] The semiconductor package further includes a plurality of first electrical routing layer contact elements 13 and a plurality of second electrical routing layer contact elements 14 on a first side 11 of the routing layer 10; and a plurality of third electrical routing layer contact elements 15 on a second side 12 of the routing layer 10 opposite the first side 11.

[028] The semiconductor package further includes a first semiconductor die 20 having a first side 21 facing the first side 11 of the routing layer 10, and a second side 22 opposite the first side 21 of the first semiconductor die 20; a plurality of first electrical die contact elements 23 on the first side 21 of the first semiconductor die 20; and a plurality of second electrical die contact elements 24 on the first side 21 of the first semiconductor die 20.

[029] The semiconductor package further includes a second semiconductor die 30 having a first side 31 facing the first side 11 of the routing layer 10, and a second side 32 opposite the first side 31 of the second semiconductor die 30; a plurality of third electrical die contact elements 33 on the first side 31 of the second semiconductor die 30; and a plurality of fourth electrical die contact elements 34 on the first side 31 of the second semiconductor die 30.

[030] The semiconductor package further includes an interconnection die 40 having a first side 41, and a second side 42 opposite the first side 41; wherein a first portion 47 of the first side 41 faces at least a portion 25 of the first side 21 of the first semiconductor die 20 and a second portion 48 of the first side 41 faces at least a portion 35 of the first side 31 of the second semiconductor die 30; and wherein the second side 42 faces the first side 11 of the routing layer 10; a plurality of fifth electrical die contact elements 43 on the first portion 47 of the first side 41 of the interconnection die 40; and a plurality of sixth electrical die contact elements 44 on the second portion 48 of the first side 41 of the interconnection die 40;

[031 ] Figure 1 shows the semiconductor packaging 1 further includes a resin encapsulation structure 50 covering at least a portion of the first semiconductor die 20, at least a portion of the second semiconductor die 30, and at least a portion of the interconnection die 40.

[032] Figure 1 shows the semiconductor packaging 1 further includes one or more first resin encapsulated electrical interconnections 51 extending vertically between the plurality of first electrical routing layer contact elements 13 and the plurality of first electrical die contact elements 23 to electrically connect the routing layer 10 and the first semiconductor die 20.

[033] Figure 1 shows the semiconductor packaging 1 further includes one or more second resin encapsulated electrical interconnections 52 extending vertically between the plurality of second electrical routing layer contact elements 14 and the plurality of third electrical die contact elements 33 to electrically connect the routing layer 10 and the second semiconductor die 30;

[034] It can also be seen in figure 1, one or more third resin encapsulated electrical interconnections 53 extending vertically between the plurality of second electrical die contact elements 24 and the plurality of fifth electrical die contact elements 43 to electrically connect the interconnection die 40 and the first semiconductor die 20; and one or more fourth resin encapsulated electrical interconnections 54 extending vertically between the plurality of fourth electrical die contact elements 34 and the plurality of sixth electrical die contact elements 44 to electrically connect the interconnection die 40 and the second semiconductor die 30.

[035] Further, figure 1 shows that the routing layer 10 includes one or more electrically conductive routing layer interconnections 17 electrically coupling one or more of the plurality of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13, and one or more of the plurality of third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14.

[036] Also, it can be seen in figure 1 that the interconnection die 40 includes one or more electrically conductive interconnection die interconnections 46 electrically connecting the plurality of fifth electrical die contact elements 43 and the plurality of sixth electrical die contact elements 44.

[037] The features of this embodiment as shown in figure 1 can be applied to various embodiments of the invention.

[038] In various embodiments, the semiconductor structure 01 includes a plurality of seventh electrical die contact elements 45 on the second side 42 of the interconnection die 40, and a plurality of fourth electrical routing layer contact elements 16 on the first side 11 of the routing layer 10. An example of that is given in connection with Figure 7.

[039] In various embodiments, the semiconductor structure 01 includes one or more backside interconnections 60 extending between the plurality of fourth electrical routing layer contact elements 16 and the plurality of seventh electrical die contact elements 45 to electrically connect the interconnection die 40 and the routing layer 10. An example of that is given in connection with Figure 7.

[040] In various embodiments, the plurality of first electrical routing layer contact elements 13, the plurality of second electrical routing layer contact elements 14, and the plurality of fourth electrical routing layer contact elements 16 are substantially along a common plane 61.

[041] In various embodiments, the interconnection die 40 is an embedded fine-pitch interconnect (EFI) die. The EFI includes single or multiple metal layers on a front side of a Si substrate. The metal layers can be fabricated by standard BEOL (backend of line) process which is commonly used for most advanced CMOS devices. This allows to make interconnects with fine line and space (L/S) pitch less than 1 micrometer or even below. Through silicon vias (TSV) are not required.

[042] In various embodiments, the interconnection die 40 includes an active device.

[043] The invention also provides a semiconductor package containing embedded fine- pitch interconnect(s) (EFI), and/or active devices, attached to two dies as a bridge.

[044] In various embodiments, the interconnection die 40 includes a silicon substrate 49.

[045] In various embodiments, the each of the one or more first resin encapsulated electrical interconnections 51 or each of the one or more second resin encapsulated electrical interconnections 52 is longer than each of the one or more third resin encapsulated electrical interconnections 43 or each of the one or more fourth resin encapsulated electrical interconnections 54.

[046] In various embodiments, the interconnection die 40 is between the routing layer 10 and a plane including a lateral arrangement including the first semiconductor die 20 and the second semiconductor die 30.

[047] In various embodiments, the plurality of first electrical die contact elements 23 and the plurality of third electrical die contact elements 33 are along a first plane 63; and wherein the plurality of second electrical die contact elements 24 and the plurality of fourth electrical die contact elements 34 are along a second plane 64. The first plane 63 and the second plane 64 are preferably each independently lower than plane 61. Such planes can be seen, for example, in figure 8.

[048] In various embodiments, a minimum pitch of the one or more electrically conductive routing layer interconnections 17 is equal or less than 5 micrometer / 5 micrometer line/space (L/S). It means that the minimum distance between two lines can be less than 5 micrometers, it also means that the width of a line can be less than 5 micrometers.

[049] In various embodiments, the first semiconductor die 20, the second semiconductor die 30 and the interconnection die 40 are on a same side of the routing layer 10. [050] FIG. 2 shows a schematic illustrating the semiconductor package 01 according to figure 1 attached to a PCB 03. It is shown that third electrical routing layer contact elements 15 of the routing layer 10 are electrically connected to the PCB 70 via solder bumps 66. The solder bumps 66 are e.g. placed on the second side 12 of the routing layer 10 before placing the semiconductor package 01 on the PCB 70.

[051] FIG. 3 shows a schematic illustrating another semiconductor package 01 according to various embodiments. It is shown a semiconductor package 01 on a PCB 70. The semiconductor package 01 includes a first semiconductor die 20 and a second semiconductor die 30. The first and second semiconductor dies are each electrically connected to the routing layer 10, and also electrically connected to each other via the interconnection die 40. The package 01 of figure 3 further includes a third semiconductor die 68 and a fourth semiconductor die 69. These third and fourth semiconductor dies can arranged and electrically connected in analogous manner as described for the first semiconductor die and the second semiconductor die throughout of the invention. The third semiconductor die may be a further first semiconductor die. The fourth semiconductor die may be a further second semiconductor die. Also, a further interconnection die 67 can be arranged and function in an analogous manner as described for the interconnection die 40 throughout of the invention. Figure 3 shows in an exemplary manner, that the third semiconductor die is electrically connected to the routing layer 10. Figure 3 also shows in exemplary manner, that the second semiconductor die 30 and the fourth semiconductor die 69 are electrically connected to each other via the further interconnection die 67. The skilled in the art would understand that the appropriate electrical contact elements and resin encapsulated electrical interconnections are provided for such arrangement.

[052] With the use of the interconnection dies and the routing layer, it is possible to provide for various different electrical paths, as exemplary shown by connections 71-76. For 71-76, the term "connections" is meant that the end points communicate electronically via such connections.

[053] In various embodiments, connections are selected from: semiconductor die to PCB (71, 72, 73), semiconductor die to semiconductor die (74), interconnection die to interconnection die (75), interconnection die to semiconductor die (76), interconnection die to PCB (77), and combinations thereof. [054] Examples of purpose for such connections are:

[055] The semiconductor package and the method of fabricating the same according to figure 3 has a greater flexibility on electrical routing and provides many possible electrical connections which utmost important in multi-die system design.

[056] The invention also concerns a method for forming a semiconductor package.

[057] Figure 4 shows a flow diagram illustrating a method for forming a semiconductor package. In various embodiments of the invention, the method includes the processes as explained in the following.

[058] In la, the method includes providing a first semiconductor die 20 having a first side 21, and a second side 22 opposite the first side 21; the first semiconductor die 20 including a plurality of first electrical die contact elements 23 on the first side 21, and a plurality of second electrical die contact elements 24 on the first side 21.

[059] In lb, the method also includes providing a second semiconductor die 30 having a first side 31, and a second side 32 opposite the first side 31; the second semiconductor die 30 including a plurality of third electrical die contact elements 33 on the first side 31, and a plurality of fourth electrical die contact elements 34 on the first side 31.

[060] lc is optional, as the interconnection die 40 can be provided with the required configuration, for example it can be pre-fabricated and stored, or it can be formed in the same manufacturing site to then be provided in the semiconductor package 01.

[061] In Id, the method also includes providing an interconnection die 40 having a first side 41, and a second side 42 opposite the first side 41, and wherein the interconnection die 40 further includes a plurality of fifth electrical die contact elements 43 on the first portion 47 of the first side 41 ; and a plurality of sixth electrical die contact elements 44 on the second portion 48 of the first side 41; and wherein the interconnection die 40 further includes one or more electrically conductive interconnection die interconnections 46 electrically connecting the plurality of fifth electrical die contact elements 43 and the plurality of sixth electrical die contact elements 44; wherein a first portion 47 of the first side 41 faces at least a portion 25 of the first side 21 of the first semiconductor die 20 and a second portion 48 of the first side 41 faces at least a portion 35 of the first side 31 of the second semiconductor die 30.

[062] In le, the method also includes forming one or more first resin encapsulated electrical interconnections 51 extending from the plurality of first electrical die contact elements 23.

[063] In If, e.g. at the same time of le, the method also includes forming one or more second resin encapsulated electrical interconnections 52 extending from the plurality of third electrical die contact elements 33.

[064] In lg, the method also includes forming one or more third resin encapsulated electrical interconnections 53 extending vertically between the plurality of second electrical die contact elements 24 and the plurality of fifth electrical die contact elements 43 to electrically connect the interconnection die 40 and the first semiconductor die 20; and forming one or more fourth resin encapsulated electrical interconnections 54 extending vertically between the plurality of fourth electrical die contact elements 34 and the plurality of sixth electrical die contact elements 44 to electrically connect the interconnection die 40 and the second semiconductor die 30;

[065] In lh, the method also includes forming a resin encapsulation structure 50 covering at least a portion of the first semiconductor die 20, at least a portion of the second semiconductor die 30, and at least a portion of the interconnection die 40.

[066] In li, the method includes forming a routing layer including one or more dielectric materials, a plurality of first electrical routing layer contact elements 13 and a plurality of second electrical routing layer contact elements 14 on a first side 11 of the routing layer 10, and a plurality of third electrical routing layer contact elements 15 on a second side 12 of the routing layer 10 opposite the first side 11. The routing layer 10 is formed so that the first side 11 faces the first side 21 of the first semiconductor die 20, and so that the first side of the routing layer 10 faces the first side 31 of the second semiconductor die 30, and further so that the first side 11 of the routing layer 10 faces the second side 42 of the interconnection die 40. Wherein the routing layer is formed so to be arranged in relation to the plurality of first electrical die contact elements 23 of the first semiconductor die 20 to electrically connect the routing layer 10 and the first semiconductor die 20, and in relation to the plurality of third electrical die contact elements 33 of the second semiconductor die 30 to electrically connect the routing layer 10 and the second semiconductor die 30. The routing layer includes one or more electrically conductive routing layer interconnections 17 electrically coupling one or more of the plurality of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13. and one or more of the plurality of third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14;

[067] The combination of forming a resin layer 55 and removing the excess, is advantageous, since it creates a very flat layer, thus allowing the use of high resolution lithography for creating the routing layer.

[068] In various embodiments, the routing layer 10 is fabricated over the grinded resin layer. For example, the routing layer 10 may be formed by forming a plurality of metallization layers 17 separated by dielectric layers. The plurality of metallization layers 17 are e.g. patterned into conductive traces that are vertically connected by vertical interconnections, such as through mold vias, Cu or Au pillars, Cu or Au wires. An exemplary pitch of a metal layer segment of the plurality of metallization layers segment could be 6um

[069] la and lb could be reversed, or both could be realized at the same time.

[070] The skilled person in the art would understand from the present disclosure that the processes may be realized in a different order as presented above. For instance, lb may be realized right before Id, or any time before any of la to Id, for example, the interconnection die 20 may be produced elsewhere and only provided from the stock when necessary for producing the semiconductor packaging.

[071] The first side 21 of the first semiconductor 20 and the first side 31 of the second semiconductor die are e.g. coplanar. Additionally, the second side 22 of the first semiconductor 20 and the second side 32 of the second semiconductor die are e.g. coplanar. [072] In various embodiments, the one or more first resin encapsulated electrical interconnections 51 and the one or more second resin encapsulated electrical interconnections 52 are e.g. selected from at least one of stud bumps or through any other mold interconnects.

[073] Through mold interconnects - can be any other suitable means of electrical connection, such as stud bumping by wire bonder, solder balls, Cu pillars by electroplating, laser drilled through mold vias with metallization by electroplating etc.

[074] In various embodiments, it is preferred that the first semiconductor die 20 and the second semiconductor die 30 are provided on a carrier 70 and the second side of the first semiconductor die 20 and the second side of the second semiconductor die 30 face the carrier. In various embodiments, it is preferred that the first semiconductor die 20 and the second semiconductor die 30 are provided on a carrier 70 before, the one or more first resin encapsulated electrical interconnections 51 are formed on the first semiconductor die 20 and the one or more second resin encapsulated electrical interconnections 52 are formed on the second semiconductor die 30.

[075] In various embodiments, the semiconductor structure e.g. includes at least one further first semiconductor die, at least one further second semiconductor die and at least one further interconnection die.

[076] In various embodiments, the forming the resin encapsulation structure 50 e.g. include depositing a mold compound material, and back grinding the encapsulation material to expose one or more first resin encapsulated electrical interconnections 51, and one or more second resin encapsulated electrical interconnections 52. Additionally, in various embodiments, the forming the resin encapsulation structure 50 e.g. includes depositing a mold compound material, and back grinding the encapsulation material to expose the second side 42 of the interconnection die 40.

[077] In various embodiments, the method e.g. further includes forming a plurality of seventh electrical die contact elements 45 on the second side 42 of the interconnection die 40 before forming the routing layer 10, and forming one or more backside interconnections on the plurality of seventh electrical die contact elements. Additionally, the method e.g. includes forming a plurality of fourth electrical routing layer contact elements 16 on the first side 11 of the routing layer 10 to connect the one or more backside interconnections.

[078] FIG. 5A and 5B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments. In 5. a (not shown) the first semiconductor die 20 and the second semiconductor die 30 are provided. A first semiconductor die 20 with a first side 21 and a second side 22 is provided, wherein the first side includes first electrical die contact elements 23 and second electrical die contact elements 24. The second electrical die contact elements 24 are comprised on portion 25 of the first side 21. A second semiconductor die 30 with a first side 301 and a second side 32 is provided, wherein the first side includes third electrical die contact elements 33 and fourth electrical die contact elements 34. The fourth electrical die contact elements 34 are comprised on portion 35 of the first side 31.

[079] The first resin encapsulated electrical interconnections 51 are provided on first side

21 of the first semiconductor die 20 and the second resin encapsulated electrical interconnections 52 are provided on the first side 31 of the second semiconductor die 30, before the first semiconductor die 20 and the second semiconductor die 30 are attached to carrier 70. The interconnections 51 and 52 can be fabricated on the dies 20 and 30 or the dies can be provided with the finished interconnections.

[080] In 5,b, the second side 22 of the second semiconductor die 20 and the second side 32 of the second semiconductor die 30 are attached to the same side of the carrier 70. A portion 35 of the first side 31 of the second semiconductor die 30 includes fourth electrical die contact elements 34. A portion 25 of the first side 21 of the second semiconductor die 22 includes second electrical die contact elements 24.

[081] In 5.c an interconnection die 40 with a first side 41 and a second side 42 is provided wherein the first side 41 is facing the portion 35 of the first side 31 of the second semiconductor die 30 and the portion 25 of the first side 21 of the second semiconductor die 22. The first side 41 of the interconnection die 40 includes a first portion 47 including fifth electrical die contact elements 43, and a second portion 48 including the sixth electrical die contact elements 44. The second electrical die contact elements 24 on the first side 21 of the first semiconductor die 20 are electrically contacted to the fifth electrical die contact elements 43 on the first portion 47 of the first side 41 of the interconnection die 40 e.g. by the third resin encapsulated electrical interconnections 53.

[082] The fourth electrical die contact elements 34 on the first side 31 of the second semiconductor die 32 are electrically connected to the sixth electrical die contact elements 44 on the second portion 48 of the first side 41 of the interconnection die 40 e.g. by the fourth resin encapsulated electrical interconnections 54. [083] In various embodiments, the third resin encapsulated electrical interconnections 53 are solder bumps.

[084] In various embodiments, the fourth resin encapsulated electrical interconnections 54 are solder bumps.

[085] The electrical connection, for example solder joints, can be performed at the same time of positioning the die, or at a later stage, preferably by solder reflow, but is performed, e.g. before the encapsulation step 5.d.

[086] In 5.d, a resin layer 55 is formed covering at least a portion of the first die 20, the second die 30, and the interconnection die 40, e.g. encapsulating the first die 20, the second die 30, and the interconnection die 40 into an intermediate product. A preferred method for the encapsulation is molding. In this process, the resin encapsulated electrical interconnections, e.g. first 51, second 52, are encapsulated, hence the name "encapsulated" electrical interconnections as used throughout this specification.

[087] In 5.e, the overmold of the resin layer 55 is partially removed, for example by grinding so as to expose part of the first resin encapsulated electrical interconnections 51 and part of the second resin encapsulated electrical interconnections 52, so that these can be electrically connected in the next processes. The term "overmold" means an excess of resin that is not required in the final product, and is only available in the intermediate product of 5.d (or equivalent process in other embodiments), and removed in 5.e (or equivalent process in other embodiments).

[088] The combination of forming a resin layer 55 and removing the excess, is advantageous, since it creates a very flat layer, thus allowing the use of high resolution lithography for creating the routing layer. In various embodiments, the routing layer includes redistribution layers (RDLs), the redistribution layers have a fine L/S as low as <2micrometers. Such fine-pitch RDL cannot be fabricated on conventional organic substrate. In addition, this invention can achieve low-cost assembly process for 2.5D/3D package, since organic substrate underfill and through-silicon vias are not necessary at this side of the semiconductor package.

[089] The resin also provides advantages such as environmental protection for ten embedded interconnection die 40, the fourth resin encapsulated electrical interconnections 54 between sixth electrical die contact elements 44 and fourth electrical die contact elements 34, and the third resin encapsulated electrical interconnections 53 between fifth electrical die contact elements 43 and second electrical die contact elements 24. [090] In 5.f, the routing layer 10 is formed. The routing layer 10 includes a first side 11 and a second side 12 opposite the first side 11. The routing layer 10 is formed to include first electrical routing layer contact elements 13 on the first side 12 of the routing layer 10 and a second electrical routing layer contact elements 14 on the first side 12 of the routing layer 10. The routing layer 10 is formed to further include third electrical routing layer contact elements 15 on the second side 12. The routing layer 10 further includes routing-layer interconnections 17 electrically coupling of the of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13 contact elements, and one or more of the third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14. For example, the routing layer 10 may be formed by forming a plurality of metallization layers 17 separated by dielectric layers. The plurality of metallization layers 17 are e.g. patterned into conductive traces that are vertically connected by vertical interconnections, such as through mold vias, Cu or Au pillars, Cu or Au wires. An exemplary pitch of a metal layer segment of the plurality of metallization layers segment could be 6 micrometers.

[091] In 5.g ₅ the solder bumps 66 are placed on the third electrical routing layer contact elements 15. The carrier 70 may be removed before or after, e.g. after, placing the solder bumps.

[092] The thus finished semiconductor package 01 can now be soldered to a PCB as shown, e.g., in Figure 2. Notice that the package 01 is flipped over to be soldered to the PCB, the PCB is conventionally shown drawn at the bottom, because that also corresponds to the usual position in a manufacturing process.

[093] FIG. 6A and 6B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments.

[094] A first semiconductor die 20 with a first side 21 and a second side 22 is provided, wherein the first side includes first electrical die contact elements 23 and second electrical die contact elements 24. The second electrical die contact elements 24 are comprised on portion 25 of the first side 21. A second semiconductor die 30 with a first side 301 and a second side 32 is provided, wherein the first side includes third electrical die contact elements 33 and fourth electrical die contact elements 34. The fourth electrical die contact elements 34 are comprised on portion 35 of the first side 31. [095] In 6.a, the second side 22 of the second semiconductor die 20 and the second side 32 of the second semiconductor die 30 are attached to the same side of the carrier 70.

[096] In 6.b the first resin encapsulated electrical interconnections 51 are fabricated on first side 21 of the first semiconductor die 20 and the second resin encapsulated electrical interconnections 51 and 52 are fabricated on the first side 31 of the second semiconductor die 30. Thus, the interconnections 51 and 52 are made after the first semiconductor die 20 and the second semiconductor die 30 are attached to carrier 70.

[097] A portion 35 of the first side 31 of the second semiconductor die 30 includes fourth electrical die contact elements 34. A portion 25 of the first side 21 of the second semiconductor die 22 includes second electrical die contact elements 24. The interconnections 51 and 52 are not formed on these portions 35 and 34. These portions will be needed in a following process for other connections.

[098] In 6. c an interconnection die 40 with a first side 41 and a second side 42 is provided wherein the first side 41 is facing the portion 35 of the first side 31 of the second semiconductor die 30 and the portion 25 of the first side 21 of the second semiconductor die 22. The first side 41 of the interconnection die 40 includes a first portion 47 including fifth electrical die contact elements 43, and a second portion 48 including the sixth electrical die contact elements 44. The second electrical die contact elements 24 on the first side 21 of the first semiconductor die 20 are electrically contacted to the fifth electrical die contact elements 43 on the first portion 47 of the first side 41 of the interconnection die 40 e.g. by the third resin encapsulated electrical interconnections 53.

[099] The fourth electrical die contact elements 34 on the first side 31 of the second semiconductor die 32 are electrically connected to the sixth electrical die contact elements 44 on the second portion 48 of the first side 41 of the interconnection die 40 e.g. by the fourth resin encapsulated electrical interconnections 54.

[100] In various embodiments, the third resin encapsulated electrical interconnections 53 are solder bumps.

[101] In various embodiments, the fourth resin encapsulated electrical interconnections 54 are solder bumps.

[102] The electrical connection, for example solder joints, can be performed at the same time of positioning the die, or at a later stage, preferably by solder reflow, but is performed, e.g. before the encapsulation step 5.d. [103] In 6.d, a resin layer 55 is formed covering at least a portion of the first die 20, the second die 30, and the interconnection die 40, e.g. encapsulating the first die 20, the second die 30, and the interconnection die 40 into an intermediate product. A preferred method for the encapsulation is molding.

[104] In 6.e, the overmold of the resin layer 55 is partially removed, for example by grinding, so as to expose part of the first resin encapsulated electrical interconnections 51 and part of the second resin encapsulated electrical interconnections 52, so that these can be electrically connected in the next processes.

[105] The combination of forming a resin layer 55 and removing the excess, is advantageous, since it creates a very flat layer, thus allowing the use of high resolution lithography for creating the routing layer. In various embodiments, the routing layer includes redistribution layers (RDLs), the redistribution layers have a fine L/S as low as <2micrometers. Such fine-pitch RDL cannot be fabricated on conventional organic substrate. In addition, this invention can achieve low-cost assembly process for 2.5D/3D package, since organic substrate underfill and through-silicon vias are not necessary at this side of the semiconductor package.

[106] The resin also provides advantages such as environmental protection for ten embedded interconnection die 40, the fourth resin encapsulated electrical interconnections 54 between sixth electrical die contact elements 44 and fourth electrical die contact elements 34, and the third resin encapsulated electrical interconnections 53 between fifth electrical die contact elements 43 and second electrical die contact elements 24.

[107] In 6.f, the routing layer 10 is formed. The routing layer 10 includes a first side 11 and a second side 12 opposite the first side 11. The routing layer 10 is formed to include first electrical routing layer contact elements 13 on the first side 12 of the routing layer 10 and a second electrical routing layer contact elements 14 on the first side 12 of the routing layer 10. The routing layer 10 is formed to further include third electrical routing layer contact elements 15 on the second side 12. The routing layer 10 further includes routing-layer interconnections 17 electrically coupling of the of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13 contact elements, and one or more of the third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14. For example, the routing layer 10 may be formed by forming a plurality of metallization layers 17 separated by dielectric layers. The plurality of metallization layers 17 are e.g. patterned into conductive traces that are vertically connected by vertical interconnections, such as through mold vias, Cu or Au pillars, Cu or Au wires. An exemplary pitch of a metal layer segment of the plurality of metallization layers segment could be 6 micrometers.

[108] In 6.g, the solder bumps 66 are placed on the third electrical routing layer contact elements 15. The carrier 70 may be removed before or after, e.g. after, placing the solder bumps.

[109] The thus finished semiconductor package 01 can now be soldered to a PCB as shown, e.g., in Figure 2. Notice that the package 01 is flipped over to be soldered to the PCB, the PCB is conventionally shown drawn at the bottom, because that also corresponds to the usual position in a manufacturing process.

[110] FIG. 7A and 7B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments.

[I l l] A first semiconductor die 20 with a first side 21 and a second side 22 is provided, wherein the first side includes first electrical die contact elements 23 and second electrical die contact elements 24. The second electrical die contact elements 24 are comprised on portion 25 of the first side 21. A second semiconductor die 30 with a first side 301 and a second side 32 is provided, wherein the first side includes third electrical die contact elements 33 and fourth electrical die contact elements 34. The fourth electrical die contact elements 34 are comprised on portion 35 of the first side 31.

[112] In 7. a, the second side 22 of the second semiconductor die 20 and the second side 32 of the second semiconductor die 30 are attached to the same side of the carrier 70.

[113] In 7.b the first resin encapsulated electrical interconnections 51 are fabricated on first side 21 of the first semiconductor die 20 and the second resin encapsulated electrical interconnections 51 and 52 are fabricated on the first side 31 of the second semiconductor die 30. Thus, the interconnections 51 and 52 are made after the first semiconductor die 20 and the second semiconductor die 30 are attached to carrier 70.

[114] A portion 35 of the first side 31 of the second semiconductor die 30 includes fourth electrical die contaet elements 34. A portion 25 of the first side 21 of the second semiconductor die 22 includes second electrical die contact elements 24. The interconnections 51 and 52 are not formed on these portions 35 and 34. These portions will be needed in a following process for other connections. [115] In 7. c an interconnection die 40 with a first side 41 and a second side 42 is provided wherein the first side 41 is facing the portion 35 of the first side 31 of the second semiconductor die 30 and the portion 25 of the first side 21 of the second semiconductor die 22. The first side 41 of the interconnection die 40 includes a first portion 47 including fifth electrical die contact elements 43, and a second portion 48 including the sixth electrical die contact elements 44. The second electrical die contact elements 24 on the first side 21 of the first semiconductor die 20 are electrically contacted to the fifth electrical die contact elements 43 on the first portion 47 of the first side 41 of the interconnection die 40 e.g. by the third resin encapsulated electrical interconnections 53.

[116] As with any other embodiment of the invention, any, including the interconnection die 40, is e.g. made on s substrate 49, which is e.g. Si. e.g. the interconnection die is attached to the semiconductor dies (20, 30, or other) with the substrate facing away from the semiconductor dies.

[117] The fourth electrical die contact elements 34 on the first side 31 of the second semiconductor die 32 are electrically connected to the sixth electrical die contact elements 44 on the second portion 48 of the first side 41 of the interconnection die 40 e.g. by the fourth resin encapsulated electrical interconnections 54.

[118] In various embodiments, the third resin encapsulated electrical interconnections 53 are solder bumps.

[119] In various embodiments, the fourth resin encapsulated electrical interconnections 54 are solder bumps.

[120] The electrical connection, for example solder joints, can be performed at the same time of positioning the die, or at a later stage, preferably by solder reflow, but is performed, e.g. before the encapsulation step 5.d.

[121] In 7.d, a resin layer 55 is formed covering at least a portion of the first die 20, the second die 30, and the interconnection die 40, e.g. encapsulating the first die 20, the second die 30, and the interconnection die 40 into an intermediate product. A preferred method for the encapsulation is molding.

[122] In 7.e, the overmold of the resin layer 55 is partially removed, for example by grinding. In this variation of the invention, removing part of the resin layer has at least two functions. One function is to expose part of the first resin encapsulated electrical interconnections 51 and part of the second resin encapsulated electrical interconnections 52, so that these can be electrically connected in the next processes. Another function is to expose the substrate 49 of the interconnection die 40.

[123] After exposing the substrate 49 of the interconnection die 40, the substrate may be completely etched away, thus exposing the second side 42 of the interconnection die 40 and the seventh electrical die contact elements 45 on the second side 42 of the interconnection die 40. This enables additional connection paths through the interconnection die 40 (or another interconnection die) resulting design flexibility. Part of I/Os and/or power & ground from the first semiconductor die 20 (second semiconductor die 30, or another semiconductor die) can be connected via interconnection die 40 (or another respective interconnection die).

[124] e.g. before 7.f, backside interconnections 60 are provided, extending from the seventh electrical die contact elements 45 for contacting with the fourth electrical routing layer contact elements 16 to electrically connect the interconnection die 40 and the routing layer 10, when the routing layer 10 is formed.

[125] In 7.f, the routing layer 10 is formed. The routing layer 10 includes a first side 11 and a second side 12 opposite the first side 11. The routing layer 10 is formed to include first electrical routing layer contact elements 13 on the first side 12 of the routing layer 10 and a second electrical routing layer contact elements 14 on the first side 12 of the routing layer 10. The routing layer 10 is formed to further include third electrical routing layer contact elements 15 on the second side 12.

[126] The routing layer 10 further includes routing-layer interconnections 17 electrically coupling the of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13, and one or more of the third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14. In this variation of the invention, the routing layer 10 includes fourth electrical routing layer contact elements 16, and the routing-layer interconnections 17 electrically couple the electrical routing layer contact elements 16 with the third electrical routing layer contact elements 15, the first electrical routing layer contact elements 13, and/or the second electrical routing layer contact elements 14.

[127] As an example, the routing layer 10 may be formed by forming a plurality of metallization layers 17 separated by dielectric layers. The plurality of metallization layers 17 are e.g. patterned into conductive traces that are vertically connected by vertical interconnections, such as through mold vias, Cu or Au pillars, Cu or Au wires. An exemplary pitch of a metal layer segment of the plurality of metallization layers segment could be 6 micrometers.

[128] In 7.g, the solder bumps 66 are formed on placed on the third electrical routing layer contact elements 15. The carrier 70 may be removed before or after, e.g. after, placing the solder bumps.

[129] The thus finished semiconductor package 01 can now be soldered to a PCB as shown, e.g., in Figure 2. Notice that the package 01 is flipped over to be soldered to the PCB, the PCB is conventionally shown drawn at the bottom, because that also corresponds to the usual position in a manufacturing process.

[130] The method of figure 7A can be further modified by replacing 7.a and 7.b by 5.b of figure 5 A, thus wherein the first semiconductor die 20 and the second semiconductor die 30 are provided with the electrical interconnections 51, instead of fabricating the electrical interconnections 51 on the first semiconductor die 20 and the second semiconductor die 30 after their attachment to the substrate.

[131] In various embodiments, it is advantageous that the substrate 49 of the interconnection die 40 is removed, e.g. by etching). This reduces the overall thickness of the semiconductor package, in particular the thickness of the interconnection die. It is therefore possible to use resin encapsulated electrical interconnections (such as first resin encapsulated electrical interconnections 51, and second resin encapsulated electrical interconnections 52) with less height, e.g. the resin encapsulated electrical interconnections have a height of below 50 micrometers. Additionally or alternative, the resin encapsulated electrical interconnections are metal pillars including mainly Cu. Such are especially suitable for high I/O counts more than 1000 pins for example.

[132] In various embodiments, the term semiconductor die has the common meaning in the art. e.g. the first semiconductor e.g. die includes a processing using, such as a central processing unit (CPU) or a graphic processing unit (GPU), and the second semiconductor die e.g. includes a memory. In various embodiments, it is preferred that at least one semiconductor die, e.g. the second semiconductor die is a high band width (HBM) memory. The word "memory" herein means that a die that includes the storage circuit and e.g. includes the auxiliary circuit such as the memory controller on the same die.

[133] The present invention is especially advantageous for semiconductor die(s) that require high density inter-chip connections, such as HBM, which requires high density inter- chip connections between CPU/GPU and HBM of over 1000 lines per several millimeters. The present invention enables this high density inter-chip connections without using expensive additional components such as Si interposer with TSVs.

[134] In various embodiments, the material of the carrier 70 is e.g. selected from Si, glass or ceramics.

[135] In various embodiments, the any of the semiconductor dies, at least the first die 20 and the second die 30, are e.g. attached to the carrier with an adhesive material, such as a die attach film.

[136] The interconnection die, and e.g. any further interconnection die according to the invention, is bonded to the first and second semiconductor dies with flip-chip bonding. The connection pitch can be reduced such as <50micrometer range, providing much higher connection density as compared with boding on to organic substrate.

[137] In various embodiments, the term "interconnection die" refers to a die, including a substrate, which substrate includes single or multiple metal layers on at least one side of the substrate. The die is preferably a Si die and the substrate a Si substrate. The interconnection die(s) is(are) e.g. an embedded fine-pitch interconnect (EFI). The metal layers can be fabricated by standard BEOL (backend of line) process which is commonly used for most advanced CMOS devices. This allows to make interconnects with fine line and space (L/S) pitch less than 1 micrometer or even below. Through silicon vias (TSV) are not required.

[138] In various embodiments, the encapsulated electrical interconnections are e.g. through mold interconnections (TMIs). In various embodiments, the interconnections 51 and 52 are stud bumps, e.g. including mainly: Cu, Au, Al, or a suitable combination thereof. Alternatively, the interconnections 51 and 52 are metal pillars, such as Cu-pillars. Such pillars can have a high aspect ratio and fine-pitch. This also applies to other interconnections in semiconductor packages having additional semiconductor dies according to the invention.

[139] In flip-chip bonding, the solder dots (or bumps, or balls) are provided on the metallized contact elements of the interconnection die, the die 40 is positioned so that the solder dots face the electrical contacts of the dies 20 and 30. Thereafter the solder dots are remelted, joining the electrical contacts of the die 40 with die 20 or 30.

[140] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

List of Reference Numbers

01 semiconductor package

02 dielectric materials

03 PCB (Printed Circuit Board)

10 routing layer

11 first side of the routing layer

12 second side of the routing layer opposite the first side

13 first electrical routing layer contact elements on the first side of the routing layer

14 second electrical routing layer contact elements on the first side of the routing layer

15 third electrical routing layer contact elements

16 fourth electrical routing layer contact elements

17 routing-layer interconnections

20 first semiconductor die

21 first side of the first semiconductor die

22 second side of the first semiconductor die

23 first electrical die contact elements on the first side of the first semiconductor die

24 second electrical die contact elements on the first side of the first semiconductor die

25 portion of the first side of the first semiconductor die

30 second semiconductor die

31 first side of the second semiconductor die

32 second side of the second semiconductor die third electrical die contact elements on the first side of the second semiconductor die fourth electrical die contact elements on the first side of the second semiconductor die portion of the first side of the second semiconductor die

interconnection die

first side of the interconnection die

second side of the interconnection die

fifth electrical die contact elements on the first portion of the first side of the interconnection die

sixth electrical die contact elements on the second portion of the first side of the interconnection die

seventh electrical die contact elements on the second side of the interconnection die interconnection-die interconnections

first portion of the first side of the interconnection die

second portion of the first side of the interconnection die

substrate

resin encapsulation structure

first resin encapsulated electrical interconnections

second resin encapsulated electrical interconnections

third resin encapsulated electrical interconnections fourth resin encapsulated electrical interconnections resin that will be backgrinded

backside interconnections solder bumps further interconnection die third semiconductor die fourth semiconductor die Carrier

-76 connections