Title:
SEMICONDUCTOR PACKAGE, SEMICONDUCTOR MODULE, ELECTRONIC DEVICE, AND SEMICONDUCTOR PACKAGE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2024/062719
Kind Code:
A1
Abstract:
Disclosed herein is a semiconductor package including a semiconductor chip configured to have one of two surfaces thereof mounted with a circuit, the circuit formation surface constituting a circuit formation surface, a first shield layer configured to cover a side of the semiconductor chip and the other surface thereof, and a second shield layer configured to cover the circuit formation circuit.
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| WO/2023/070581 | FAN-OUT CHIP PACKAGING STRUCTURE AND PREPARATION METHOD |
| WO/2017/164873 | ELECTRICAL DEVICES AND METHODS FOR FORMING ELECTRICAL DEVICES |
| JPS587848 | INTEGRATED CIRCUIT |
Inventors:
YASUKAWA HIROHISA (JP)
SHIGETA HIROYUKI (JP)
SHIGETA HIROYUKI (JP)
Application Number:
PCT/JP2023/024723
Publication Date:
March 28, 2024
Filing Date:
July 04, 2023
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L23/552; H01L25/065; H01L23/00; H01L23/13; H01L23/498; H01L23/50; H01L25/16
Foreign References:
| US10008454B1 | 2018-06-26 | |||
| US20170330839A1 | 2017-11-16 | |||
| US20140084477A1 | 2014-03-27 | |||
| JP2022180705A | 2022-12-07 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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