Title:
SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD FOR PRODUCING SAME
Document Type and Number:
WIPO Patent Application WO/2020/105633
Kind Code:
A1
Abstract:
The present invention comprises a first principal surface on which a semiconductor device is mounted, and a second principal surface for forming an external connection terminal for electrically connecting to a printed wiring board. A first wiring layer is formed in one or more layers on the first principal surface side. The first wiring layer is provided with a first insulating resin layer (110) and a first conductor circuit layer (130). The first conductor circuit layer is provided with a via hole section (141) and a wiring section (142). A seed metal layer is formed on three surfaces of surfaces where the first insulating resin layer and the wiring section in the first conductor circuit layer are grounded. A second wiring layer is formed in one or more layers on the second principal surface side. The second wiring layer is provided with a second insulating resin layer (170) and with a second conductor circuit layer of a via hole section (191) and a wiring section (190). A seed metal layer is formed on only one surface of a surface where the wiring section in the second conductor circuit layer and the second insulating resin layer are grounded.
Inventors:
TAKAGI FUSAO (JP)
Application Number:
PCT/JP2019/045274
Publication Date:
May 28, 2020
Filing Date:
November 19, 2019
Export Citation:
Assignee:
TOPPAN PRINTING CO LTD (JP)
International Classes:
H01L25/18; H01L25/04; H05K3/46
Foreign References:
| JP2010157690A | 2010-07-15 | |||
| JP2011222948A | 2011-11-04 | |||
| JP2003163323A | 2003-06-06 | |||
| US20180294212A1 | 2018-10-11 | |||
| JP5558623B1 | 2014-07-23 | |||
| JP2015050315A | 2015-03-16 | |||
| JP2007242888A | 2007-09-20 |
Attorney, Agent or Firm:
HIROSE Hajime et al. (JP)
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