Title:
SEMICONDUCTOR PACKAGING WIRING SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGING WIRING SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2020/090601
Kind Code:
A1
Abstract:
Provided is a wiring substrate with which it is possible to suppress a decrease in the yield of an FC-BGA wiring board with an interposer and to mount a semiconductor chip well, and which has high reliability. A semiconductor packaging wiring substrate has an interposer 3 bonded to an FC-BGA wiring board 1. The interposer has a thickness of from 10 μm to 1000 μm, and a semiconductor chip-connecting pad 14 connected to the semiconductor chip 4 is provided on a surface of the interposer on the side opposite to the FC-BGA wiring board. The semiconductor chip-connecting pad is a stacked body of metal material with an Au layer on the uppermost surface thereof, wherein the surface of the Au layer is provided in a recess lower than the surface of a surrounding insulating resin 15 by a range of from 0.3 to 5.0 μm.
Inventors:
SAWADAISHI MASASHI (JP)
Application Number:
PCT/JP2019/041634
Publication Date:
May 07, 2020
Filing Date:
October 24, 2019
Export Citation:
Assignee:
TOPPAN PRINTING CO LTD (JP)
International Classes:
H01L23/12; H01L21/60; H01L23/32; H05K3/46
Domestic Patent References:
| WO2018047861A1 | 2018-03-15 |
Foreign References:
| JP2010129899A | 2010-06-10 |
Attorney, Agent or Firm:
PATENT CORPORATE BODY DAI-ICHI KOKUSAI TOKKYO JIMUSHO (JP)
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