Title:
SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2011/074545
Kind Code:
A1
Abstract:
Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≥1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surfaces of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
Inventors:
SASAGO YOSHITAKA (JP)
SHIMA AKIO (JP)
HANZAWA SATORU (JP)
KOBAYASHI TAKASHI (JP)
KINOSHITA MASAHARU (JP)
TAKAURA NORIKATSU (JP)
SHIMA AKIO (JP)
HANZAWA SATORU (JP)
KOBAYASHI TAKASHI (JP)
KINOSHITA MASAHARU (JP)
TAKAURA NORIKATSU (JP)
Application Number:
PCT/JP2010/072398
Publication Date:
June 23, 2011
Filing Date:
December 13, 2010
Export Citation:
Assignee:
HITACHI LTD (JP)
SASAGO YOSHITAKA (JP)
SHIMA AKIO (JP)
HANZAWA SATORU (JP)
KOBAYASHI TAKASHI (JP)
KINOSHITA MASAHARU (JP)
TAKAURA NORIKATSU (JP)
SASAGO YOSHITAKA (JP)
SHIMA AKIO (JP)
HANZAWA SATORU (JP)
KOBAYASHI TAKASHI (JP)
KINOSHITA MASAHARU (JP)
TAKAURA NORIKATSU (JP)
International Classes:
H01L27/105; H01L27/10; H01L45/00
Foreign References:
| JP2008160004A | 2008-07-10 | |||
| JP2007180389A | 2007-07-12 | |||
| JP2008034456A | 2008-02-14 | |||
| JP2009071313A | 2009-04-02 |
Other References:
H.TANAKA ET AL.: "Bit Cost scalable Technology with Punch and Plug Process", SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, - 12 June 2007 (2007-06-12), pages 14 - 15
Attorney, Agent or Firm:
TSUTSUI, YAMATO (JP)
Tsutsui Daiwa (JP)
Tsutsui Daiwa (JP)
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