Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
WIPO Patent Application WO/2012/011161
Kind Code:
A1
Abstract:
Disclosed is a semiconductor storage device which comprises: a memory cell array in which memory cells are arranged in a matrix form; and a reference resistance circuit that produces a reference resistance. A memory cell has a date storage resistance element that is a variable resistance element. The reference resistance circuit has a first reference resistance element (Rr1) and a second reference resistance element (Rr2), each of which is a variable resistance element that has the same structure as the date storage resistance element. The first reference resistance element (Rr1) is set to a first resistance, and the second reference resistance element (Rr2) is set to a second resistance that is lower than the first resistance. The reference resistance is a resistance between the first resistance and the second resistance, and is produced by connecting the first reference resistance element and the second reference resistance element with each other.
Inventors:
MIKI, Takashi (())
Application Number:
JP2010/007481
Publication Date:
January 26, 2012
Filing Date:
December 24, 2010
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
International Classes:
G11C11/15; G11C13/00; H01L21/8246; H01L27/105; H01L43/08
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
Claims:
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