Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
WIPO Patent Application WO/2012/168981
Kind Code:
A1
Abstract:
For the purpose of providing a semiconductor storage device suited to miniaturization and having reduced contact resistance, the wiring structure of a memory array (MA) is as follows. Word lines (2) and bit lines (3) are extended in parallel, the respective word lines being united with other word lines, the respective bit lines being united with other bit lines, and two bit lines disposed respectively above two of the united word lines being electrically isolated. According to this feature, it is possible to form larger contact in united portions (MLC) of the wiring, making it possible to reduce contact resistance in a memory array that is suited to miniaturization.
Inventors:
SASAGO YOSHITAKA (JP)
KINOSHITA MASAHARU (JP)
KOTABE AKIRA (JP)
KOBAYASHI TAKASHI (JP)
KINOSHITA MASAHARU (JP)
KOTABE AKIRA (JP)
KOBAYASHI TAKASHI (JP)
Application Number:
PCT/JP2011/003285
Publication Date:
December 13, 2012
Filing Date:
June 10, 2011
Export Citation:
Assignee:
HITACHI LTD (JP)
SASAGO YOSHITAKA (JP)
KINOSHITA MASAHARU (JP)
KOTABE AKIRA (JP)
KOBAYASHI TAKASHI (JP)
SASAGO YOSHITAKA (JP)
KINOSHITA MASAHARU (JP)
KOTABE AKIRA (JP)
KOBAYASHI TAKASHI (JP)
International Classes:
H01L27/105; H01L45/00
Domestic Patent References:
| WO2011074545A1 | 2011-06-23 |
Foreign References:
| JP2008160004A | 2008-07-10 | |||
| JP2008192708A | 2008-08-21 | |||
| JP2010165982A | 2010-07-29 |
Attorney, Agent or Firm:
INOUE, Manabu et al. (JP)
Manabu Inoue (JP)
Manabu Inoue (JP)
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