Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
WIPO Patent Application WO/2020/262248
Kind Code:
A1
Abstract:
Provided is a layout structure of a small area one-time-programmable (OTP) memory in which a complementary FET (CFET) is used. The OTP memory has a transistor (TP) that is a program element and a transistor (TS) that is a switch element. The transistor (TP) is a three-dimensional structure transistor, and channel sections (21b, 26b) overlap as seen in plan view. The transistor (TS) is a three-dimensional structure transistor, and channel sections (21a, 26a) overlap as seen in plan view. 2 bits of OTP memory is realized in a small area.
Inventors:
YAMADA TOMOYUKI (JP)
Application Number:
PCT/JP2020/024197
Publication Date:
December 30, 2020
Filing Date:
June 19, 2020
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L27/10
Domestic Patent References:
| WO2009122560A1 | 2009-10-08 |
Foreign References:
| US7715246B1 | 2010-05-11 | |||
| JP2011077159A | 2011-04-14 | |||
| JP2012009669A | 2012-01-12 | |||
| US20180151576A1 | 2018-05-31 | |||
| JP2018026565A | 2018-02-15 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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