Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/042254
Kind Code:
A1
Abstract:
A semiconductor storage device (1) comprises a memory cell array (3) in which a plurality of memory cells (MC) are connected to a bit line pair (BLT). In reading of data from the memory cell (MC), a replica bit line signal is output to a replica bit line (TRKBL) in accordance with a replica word line signal, and a sense amplifier start signal (SAE) changes in accordance with the replica bit line signal so that a sense amplifier circuit (21) is driven. In writing of data to the memory cell (MC), a low potential side of a writing subject bit line pair is set to a negative potential by a negative potential boost signal (BOOSTX) output from a negative potential generation circuit (25).
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Inventors:
MORIWAKI SHINICHI (JP)
Application Number:
PCT/JP2021/033716
Publication Date:
March 23, 2023
Filing Date:
September 14, 2021
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
G11C11/419
Foreign References:
| JP2006012240A | 2006-01-12 | |||
| JP2010218617A | 2010-09-30 | |||
| JP2012069214A | 2012-04-05 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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