Title:
SEMICONDUCTOR STORAGE ELEMENT, SEMICONDUCTOR STORAGE DEVICE, AND SEMICONDUCTOR SYSTEM
Document Type and Number:
WIPO Patent Application WO/2018/074093
Kind Code:
A1
Abstract:
[Problem] To provide a semiconductor storage element with a reduced planar area. [Solution] A semiconductor storage element comprising: a memory cell transistor, at least part of which includes a gate insulating film formed from a ferroelectric material; and a selection transistor in which one of a source and a drain is connected to a gate electrode of the memory cell transistor via a connection layer, and in which a gate insulating film is opposed to the gate insulating film of the memory cell transistor across the connection layer in the lamination direction.
Inventors:
TSUKAMOTO MASANORI (JP)
Application Number:
PCT/JP2017/032317
Publication Date:
April 26, 2018
Filing Date:
September 07, 2017
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L27/11587; G11C11/22; H01L27/10; H01L27/1159
Foreign References:
| JP2006253381A | 2006-09-21 | |||
| JP2009230834A | 2009-10-08 | |||
| JP2015079965A | 2015-04-23 | |||
| JPH10209389A | 1998-08-07 | |||
| JP2002524880A | 2002-08-06 | |||
| JP2001229685A | 2001-08-24 |
Attorney, Agent or Firm:
KAMEYA, Yoshiaki et al. (JP)
Download PDF: