Title:
SEMICONDUCTOR STRUCTURE HAVING BOTTOM ISOLATION AND ENHANCED CARRIER MOBILITY
Document Type and Number:
WIPO Patent Application WO/2023/040424
Kind Code:
A1
Abstract:
Illustrative embodiments provide techniques for fabricating semiconductor structures having bottom isolation and enhanced carrier mobility for both nFET and pFET devices. For example, in one illustrative embodiment, a semiconductor structure includes a semiconductor substrate, a first dielectric layer disposed on the semiconductor substrate, a bottom source/drain region disposed on the first dielectric layer and isolated from the semiconductor substrate by the first dielectric layer, a second dielectric layer disposed on the bottom source/drain region and a top source/drain region disposed on the second dielectric layer and isolated from the bottom source/drain region by the second dielectric layer. The bottom source/drain region comprises a compressive pFET epitaxy and the top source/drain region comprises a tensile nFET epitaxy.
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Inventors:
FROUGIER JULIEN (US)
XIE RUILONG (US)
CHENG KANGGUO (US)
PARK CHANRO (US)
LI JUNTAO (US)
XIE RUILONG (US)
CHENG KANGGUO (US)
PARK CHANRO (US)
LI JUNTAO (US)
Application Number:
PCT/CN2022/103664
Publication Date:
March 23, 2023
Filing Date:
July 04, 2022
Export Citation:
Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
IBM CHINA CO LTD (CN)
International Classes:
H01L21/764
Foreign References:
| CN109244033A | 2019-01-18 | |||
| US5972758A | 1999-10-26 | |||
| CN106024868A | 2016-10-12 | |||
| CN111699550A | 2020-09-22 | |||
| CN113284890A | 2021-08-20 | |||
| CN102986022A | 2013-03-20 |
Attorney, Agent or Firm:
CCPIT PATENT AND TRADEMARK LAW OFFICE (CN)
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