SEMICONDUCTOR STRUCTURE AND LAYOUT THEREOF, AND SEMICONDUCTOR DEVICE

WIPO Patent Application WO/2023/015678

A1

Provided in the present disclosure are a semiconductor structure and a layout thereof, and a semiconductor device. The semiconductor structure comprises: a plurality of spaced first conductive layers; a plurality of capacitor groups, wherein the capacitor groups are located on the first conductive layers on a one-to-one basis, each capacitor group comprises at least one capacitor, and each capacitor comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer which are sequentially stacked from bottom to top; a capacitor plate located on each of the upper electrode layers; and a second conductive layer located above the capacitor plate and connected to the capacitor plate. In the semiconductor structure, the second conductive layer is formed above the capacitor plate, and the second conductive layer is connected to the capacitor plate. In this way, in the semiconductor structure, the second conductive layer is actually parallel to two ends of the capacitor plate, that is, the second conductive layer is connected to the capacitor plate in parallel, and the resistance formed by the parallel connection of the second conductive layer and the capacitor plate is smaller than the resistance of the capacitor plate itself, thereby avoiding the problem that the performance is affected due to a large resistance, and improving the performance of the semiconductor structure.

WANG PEIHUAN (CN)

PCT/CN2021/119422

February 16, 2023

September 18, 2021

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CHANGXIN MEMORY TECH INC (CN)

G11C11/4063

US20130242643A1	2013-09-19
US20070108493A1	2007-05-17
CN111180414A	2020-05-19
US20040051131A1	2004-03-18
US20150229208A1	2015-08-13

KANGXIN PARTNERS, P.C. (CN)

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