Title:
SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2023/060754
Kind Code:
A1
Abstract:
The present application relates to a semiconductor structure and a semiconductor structure manufacturing method. The method comprises: providing a substrate on which an array area and a peripheral area are defined; on the substrate, sequentially forming a laminated structure, a first dielectric layer, a first mask layer, an anti-reflection layer and a photoresist layer; forming a first pattern by means of using a patterned photoresist layer as a mask to remove part of the first dielectric layer, first mask layer and anti-reflection layer in the array area, as well as the whole first dielectric layer, first mask layer and anti-reflection layer in the peripheral area; then patterning part of a second dielectric layer and second mask layer, which are formed on the array area and the peripheral area, so as to form a second pattern. The heights of the final array area and peripheral area match, thereby reducing a load effect, simplifying the processing flow, and reducing costs.
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Inventors:
ZHANG JIAYUN (CN)
LIU HAO (CN)
WAN QIANG (CN)
LIU HAO (CN)
WAN QIANG (CN)
Application Number:
PCT/CN2021/138636
Publication Date:
April 20, 2023
Filing Date:
December 16, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/027
Foreign References:
| CN108231770A | 2018-06-29 | |||
| CN109216167A | 2019-01-15 | |||
| US10304680B1 | 2019-05-28 | |||
| US20150115337A1 | 2015-04-30 |
Attorney, Agent or Firm:
SCIHEAD IP LAW FIRM (CN)
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