Title:
SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2024/048239
Kind Code:
A1
Abstract:
Provided are: a semiconductor substrate in which occurrence of interface resistance in a junction interface can be prevented; and a method for manufacturing the semiconductor substrate. This method for manufacturing a semiconductor substrate comprises: a damaged layer formation step for forming a damaged layer in at least one of a first joining target surface of a first semiconductor substrate or a second joining target surface of a second semiconductor substrate; a specific element introduction step for introducing a specific element into at least one of the first joining target surface and the second joining target surface; a joining step for joining the first joining target surface and the second joining target surface together to form a junction semiconductor substrate having a junction interface; and a thermal treatment step for subjecting the junction semiconductor substrate to a thermal treatment. The thermal treatment step is for causing the specific element introduced into at least one of the first semiconductor substrate and the second semiconductor substrate to move into the damaged layer.
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Inventors:
UCHIDA HIDETSUGU (JP)
Application Number:
PCT/JP2023/029247
Publication Date:
March 07, 2024
Filing Date:
August 10, 2023
Export Citation:
Assignee:
SICOXS CORP (JP)
International Classes:
H01L21/02
Domestic Patent References:
| WO2016006663A1 | 2016-01-14 |
Foreign References:
| JP2018014372A | 2018-01-25 |
Attorney, Agent or Firm:
TAKINO, Fumio et al. (JP)
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