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Title:
SEMICONDUCTOR SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2018/101367
Kind Code:
A1
Abstract:
This semiconductor substrate comprises a silicon substrate, a reaction inhibition layer, a stress generation layer and an active layer, wherein the silicon substrate, the reaction inhibition layer, the stress generation layer and the active layer are positioned in the order of silicon substrate, reaction inhibition layer, stress generation layer and active layer. The reaction inhibition layer is a nitride crystal layer which inhibits the reaction between silicon atoms and group III atoms, the stress generation layer is a nitride crystal layer which generates compressive stress, and the active layer is a nitride crystal layer which forms an electronic element. The semiconductor substrate is further provided with a SiAlN layer having silicon atoms, aluminum atoms and nitrogen atoms as the main constituent elements thereof, between the silicon substrate and the reaction inhibition layer.

Inventors:
YAMAMOTO TAIKI (JP)
OSADA TAKENORI (JP)
Application Number:
PCT/JP2017/042919
Publication Date:
June 07, 2018
Filing Date:
November 29, 2017
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Assignee:
SUMITOMO CHEMICAL CO (JP)
International Classes:
H01L21/205; C23C16/34; C23C16/42; H01L21/338; H01L29/778; H01L29/812
Domestic Patent References:
WO2011016304A12011-02-10
WO2016072521A12016-05-12
Foreign References:
JP2013145821A2013-07-25
JP2006310688A2006-11-09
JP2013021124A2013-01-31
JP2010232322A2010-10-14
JP2008171843A2008-07-24
Other References:
K. MATSUMOTO ET AL., J. VAC. SOC. JPN., vol. 54, no. 6, 2011, pages 376 - 380
See also references of EP 3550592A4
Attorney, Agent or Firm:
RYUKA IP LAW FIRM (JP)
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