Title:
SEMICONDUCTOR TEST STRUCTURE AND PREPARATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2023/273016
Kind Code:
A1
Abstract:
The present application provides a preparation method for a semiconductor test structure, comprising: providing a semiconductor structure, the semiconductor structure comprising a substrate, and a capacitor array structure on the front of the substrate, the capacitor array structure comprising multiple capacitors arranged in an array, a lower electrode of each capacitor being connected to the substrate by means of a capacitor contact structure, upper electrodes of each capacitor sharing the same capacitor plate, and the capacitor plate extending to a lower part of one side of the capacitor array structure; performing back-thinning of the semiconductor structure until the capacitor contact structure is exposed; etching a edge region of the capacitor array structure from the bottom of the obtained structure until the capacitor plate is exposed; and forming a first test pad at a bottom part of the exposed capacitor plate.
Inventors:
WANG LUGUANG (CN)
Application Number:
PCT/CN2021/124404
Publication Date:
January 05, 2023
Filing Date:
October 18, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/544; G01R27/26
Foreign References:
| CN113471174A | 2021-10-01 | |||
| CN107993949A | 2018-05-04 | |||
| CN111244065A | 2020-06-05 | |||
| CN109283410A | 2019-01-29 | |||
| US20070040205A1 | 2007-02-22 | |||
| US5684304A | 1997-11-04 | |||
| US20150206809A1 | 2015-07-23 |
Attorney, Agent or Firm:
BOXIN CHINA INTELLECTUAL PROPERTY (CN)
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