Title:
SEMICONDUCTOR WAFER INSPECTION APPARATUS AND SEMICONDUCTOR WAFER INSPECTION METHOD
Document Type and Number:
WIPO Patent Application WO/2016/098375
Kind Code:
A1
Abstract:
Provided are a semiconductor wafer inspection apparatus and a semiconductor wafer inspection method, whereby warping of a semiconductor wafer due to a temperature difference between a placing surface of a table and the semiconductor wafer can be suppressed. A prober (10) of the present invention heats, in a preheating step wherein an oven (54) is used, a semiconductor wafer W to a second temperature that is equal to or lower than a first temperature, and then places the semiconductor wafer W on a placing surface (18) of a table (20) heated to the first temperature. Consequently, since a temperature difference between the placing surface (18) of the table (20) and the semiconductor wafer W is reduced, the prober (10) can suppress semiconductor wafer warping generated just after the semiconductor wafer is placed on the placing surface (18).
Inventors:
ISHIMOTO TAKASHI (JP)
SHIGESAWA YUJI (JP)
YAMAGUCHI AKIRA (JP)
MOTOYAMA TAKASHI (JP)
TAKAHASHI TAKENORI (JP)
SHIGESAWA YUJI (JP)
YAMAGUCHI AKIRA (JP)
MOTOYAMA TAKASHI (JP)
TAKAHASHI TAKENORI (JP)
Application Number:
PCT/JP2015/070855
Publication Date:
June 23, 2016
Filing Date:
July 22, 2015
Export Citation:
Assignee:
TOKYO SEIMITSU CO LTD (JP)
International Classes:
H01L21/66; H01L21/683
Foreign References:
| JPH11330171A | 1999-11-30 | |||
| JP2013156084A | 2013-08-15 | |||
| JP2001091361A | 2001-04-06 |
Attorney, Agent or Firm:
MATSUURA, Kenzo (JP)
Kenzo Matsuura (JP)
Kenzo Matsuura (JP)
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