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Patent Searching and Data


Title:
SEMICONDUCTOR WAFER LAPPING METHOD AND SEMICONDUCTOR WAFER
Document Type and Number:
WIPO Patent Application WO/2018/042761
Kind Code:
A1
Abstract:
Provided is a semiconductor wafer lapping method with which the occurrence of a ring-shaped pattern in a nanotopography map can be suppressed. The semiconductor wafer lapping method according to the present invention is characterized by comprising: a stopping step of stopping lapping of a semiconductor wafer W; an inverting step, after the stopping step, of inverting opposing surfaces of the semiconductor wafer W with respect to an upper surface plate 10A and a lower surface plate 10B; and a resuming step, after the inverting step, of resuming the lapping of the semiconductor wafer W while the inversion of the opposing surfaces Wa, Wb is maintained.

Inventors:
HASHIMOTO Daisuke (2-1 Shibaura 1-chom, Minato-ku Tokyo 34, 〒1058634, JP)
MATAGAWA Satoshi (2-1 Shibaura 1-chom, Minato-ku Tokyo 34, 〒1058634, JP)
HASHII Tomohiro (2-1 Shibaura 1-chom, Minato-ku Tokyo 34, 〒1058634, JP)
Application Number:
JP2017/017201
Publication Date:
March 08, 2018
Filing Date:
May 01, 2017
Export Citation:
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Assignee:
SUMCO CORPORATION (2-1 Shibaura 1-chome, Minato-ku Tokyo, 34, 〒1058634, JP)
International Classes:
H01L21/304; B24B37/08
Attorney, Agent or Firm:
SUGIMURA Kenji (36F Kasumigaseki Common Gate West, 3-2-1 Kasumigasek, Chiyoda-ku Tokyo 13, 〒1000013, JP)
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