Title:
SEMICONDUCTOR WAFER POLISHING METHOD
Document Type and Number:
WIPO Patent Application WO/2011/070699
Kind Code:
A1
Abstract:
Disclosed is a semiconductor wafer polishing method comprising pressing a semiconductor wafer held by a workpiece carrier and a polishing cloth equipped by a table against each other, and in this state, supplying slurry onto the polishing cloth while rotating the workpiece carrier and the table so as to polish the semiconductor wafer, said method involving supplying slurry, during the above polishing, to an area where that portion of the polishing cloth which was compressed by being pressed against the semiconductor in conjunction with the rotation of the table has recovered, and causing the cloth to efficiently absorb the slurry. As a result, it is possible to suppress degradation of the surface roughness of the area in the vicinity of the center of the resulting semiconductor wafer. If the semiconductor wafer polishing method is applied to the manufacture of a semiconductor wafer, it is possible to obtain a wafer having improved surface roughness and flatness, and contribute to the improvement of the quality of a large-diameter wafer.
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Inventors:
TERAKAWA, Ryoya (2-1 Shibaura 1-chome, Minato-k, Tokyo 34, 〒1058634, JP)
寺川 良也 (〒34 東京都港区芝浦一丁目２番１号株式会社ＳＵＭＣＯ内 Tokyo, 〒1058634, JP)
寺川 良也 (〒34 東京都港区芝浦一丁目２番１号株式会社ＳＵＭＣＯ内 Tokyo, 〒1058634, JP)
Application Number:
JP2010/006026
Publication Date:
June 16, 2011
Filing Date:
October 08, 2010
Export Citation:
Assignee:
SUMCO CORPORATION (2-1 Shibaura 1-chome, Minato-ku Tokyo, 34, 〒1058634, JP)
株式会社ＳＵＭＣＯ (〒34 東京都港区芝浦一丁目２番１号 Tokyo, 〒1058634, JP)
TERAKAWA, Ryoya (2-1 Shibaura 1-chome, Minato-k, Tokyo 34, 〒1058634, JP)
株式会社ＳＵＭＣＯ (〒34 東京都港区芝浦一丁目２番１号 Tokyo, 〒1058634, JP)
TERAKAWA, Ryoya (2-1 Shibaura 1-chome, Minato-k, Tokyo 34, 〒1058634, JP)
International Classes:
B24B37/00; H01L21/304
Attorney, Agent or Firm:
MORI, Michio et al. (M. MORI PATENT OFFICE, 17-23 Higashinaniwa-cho 5-chome, Amagasaki-sh, Hyogo 92, 〒6600892, JP)
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