CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 62/608,216, filed on December 20, 2017, entitled“SILICON NANOTUBE FETS FOR ENERGY EFFICIENT ELECTRONIC SYSTEMS,” the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

TECHNICAL FIELD

[0002] Embodiments of the subject matter disclosed herein generally relate to a silicon nanotube sensor, and more specifically to a nanotube field effect transmitter-based sensor.

DISCUSSION OF THE BACKGROUND

[0003] There is currently explosive growth of Internet of Things (loT) devices, where trillions of small stand-alone sensors and devices will be interconnected and integrated, the number of devices connected to the internet is expected to grow to 20 billion by 2020. Adoption of small stand-alone sensors requires that the sensors be as efficient as possible with respect to the space occupied by the sensor.

[0004] Conventional small stand-alone sensors in the nano-scale typically require an array of laterally stacked gate all-around nanowires that occupy considerable space. Further, conventional small stand-alone sensors typically provide very limited surface area for interacting with target molecules, which results in long responses times for sensing, and in some cases not sensing target molecules that are present in the environment.

[0005] Therefore, it would be desirable to provide sensors that are space- efficient and provide quick sensing response times.

SUMMARY

[0006] According to an embodiment, there is a sensor, which includes a substrate and a nanotube structure formed on top of the substrate. A body is formed on top of the substrate and surrounds the nanotube structure. A source contact is electrically coupled to a top portion of the nanotube structure. A drain contact is arranged on top of the substrate and is electrically coupled with a bottom portion of the nanotube structure. A gate contact is arranged on top of the nanotube structure. The gate contact is electrically is isolated from the top portion of the nanotube structure and electrically coupled with a middle portion of the nanotube structure.

The top portion of the nanotube structure is exposed to an environment surrounding the sensor.

[0007] According to another embodiment, there is a method for forming a sensor. A nanotube structure is formed on top of a substrate. A drain contact is formed on top of the substrate and is electrically coupled with a bottom portion of the nanotube structure. A body is formed on top of the substrate and surrounding the nanotube structure. A gate contact is formed on top of the nanotube structure so that the gate contact is electrically isolated from a top portion of the nanotube structure and is electrically coupled with a middle portion of the nanotube structure.

A source contact is formed so that it is electrically coupled to the top portion of the nanotube structure. The top portion of the nanotube structure is exposed to an environment surrounding the sensor.

[0008] According to a further embodiment, there is a sensor system that includes a processor and a sensor coupled to the processor. The sensor includes a substrate and a nanotube structure formed on top of the substrate. A body is formed on top of the substrate and surrounds the nanotube structure. A source contact is electrically coupled to a top portion of the nanotube structure. A drain contact is arranged on top of the substrate and is electrically coupled with a bottom portion of the nanotube structure. A gate contact is arranged on top of the nanotube structure. The gate contact is electrically is isolated from the top portion of the nanotube structure and electrically coupled with a middle portion of the nanotube structure.

The top portion of the nanotube structure is exposed to an environment surrounding the sensor.

BRIEF DESCRIPTON OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one or more embodiments and, together with the description, explain these embodiments. In the drawings:

[0010] Figure 1 illustrates a three-dimensional perspective view of a nanotube field effect transmitter-based sensor according to embodiments;

[0011] Figure 2A illustrates a side view of a nanotube field effect transmitter- based sensor according to embodiments;

[0012] Figure 2B illustrates a top view of a nanotube field effect transmitter- based sensor according to embodiments;

[0013] Figure 2C illustrates a nanotube field effect transmitter-based sensor system according to embodiments;

[0014] Figure 3 illustrates a flowchart of a method for making a nanotube field effect transmitter-based sensor according to embodiments;

[0015] Figures 4A-4K illustrate three-dimensional perspective views of the manufacture of a nanotube field effect transmitter-based sensor according to embodiments;

[0016] Figure 5 illustrates a flowchart of a method for making a nanotube field effect transmitter-based sensor according to embodiments; and

[0017] Figures 6A-6FI illustrate three-dimensional perspective views of the manufacture of a nanotube field effect transmitter-based sensor according to embodiments. DETAILED DESCRIPTION

[0018] The following description of the embodiments refers to the

accompanying drawings. The same reference numbers in different drawings identify the same or similar elements. The following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims.

The following embodiments are discussed, for simplicity, with regard to a field effect transistor-based nanotube sensor. However, the embodiments discussed herein are not limited to this transistor but may be applied to other transistors.

[0019] Reference throughout the specification to“one embodiment” or“an embodiment” means that a particular feature, structure or characteristic described in connection with an embodiment is included in at least one embodiment of the subject matter disclosed. Thus, the appearance of the phrases“in one embodiment” or“in an embodiment” in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures or characteristics may be combined in any suitable manner in one or more

embodiments.

[0020] Figure 1 illustrates a three-dimensional view of a nanotube field effect transmitter-based sensor according to embodiments. The sensor 100 includes a substrate 105 and a nanotube structure 1 10 formed on top of the substrate 105. A body 1 15 is formed on top of the substrate 105 so that it surrounds the nanotube structure 1 10. A source contact 120 is electrically coupled to a top of the nanotube structure 1 10. A drain contact 125 is arranged on top of the substrate 105 and is electrically coupled with a bottom portion of the nanotube structure 1 10. A gate contact 130 is arranged on top of the nanotube structure 1 10. The gate contact 130 is electrically is isolated from the top of the nanotube structure 1 10 and electrically coupled with a middle portion of the nanotube structure 1 10. The top of the nanotube structure 1 10 is exposed to an environment surrounding the sensor 100.

In an embodiment, the drain contact 125 can be omitted and a heavily doped silicon substrate 105 can act as a back-side drain contact.

[0021] As illustrated in Figure 1 , the top of the nanotube structure 1 10 is covered only by the gate contact 130 and a portion of the source contact 120. In one example, at least 85% of the surface area of the top of the nanotube structure 1 10 is exposed to the environment surrounding the sensor, i.e., at least 85% is not obscured by any other component of the sensor. In other embodiments, at least 90% of the surface area of the top of the nanotube structure 1 10 is exposed to the environment surrounding the sensor. Thus, as will be appreciated, the sensor 100 is particularly advantageous because of the large amount of surface area exposed to the environment, which leads to a shorter sensing time compared to conventional sensors due to the larger amount of surface area that can interact with target molecules in the environment surrounding the sensor 100. This provides a high signal-to-noise ratio.

[0022] Figure 2A is a perspective view of the nanotube structure 1 10 according to embodiments. The sensor 100 is configured as a nanotube field-effect transistor (NT-FT). Accordingly, the drain region is formed by the bottom portion 1 10A of the nanotube structure 1 10, the channel region is formed by the middle portion 1 10B of the nanotube structure 1 10, and the source region is formed by the top portion 1 10C of the nanotube structure 1 10. A passage 205 is formed from the top of the nanotube structure 1 10 to the middle portion 1 10B so that the gate contact 130 is electrically coupled to the channel. In an embodiment, the top 1 10C and bottom 1 10A portions of the nanotube structure 1 10 are p-type doped and the middle portion 1 10B is n-type doped. One skilled in the art will recognize how to select particular doping concentrations to optimize performance. In an embodiment, the first 1 10A and third 1 10C portions comprise silicon oxide (S1O2) and the middle portion 1 10B comprises titanium nitride (TiN).

[0023] Figure 2B is a top view of the sensor 100. As illustrated, the passage 205 is arranged in the middle of the nanotube structure 1 10. The body 1 15 comprises a gate dielectric 210 surrounding the nanotube structure 210 and a spacer 215 surrounding the gate dielectric. In an embodiment, the spacer can comprise, for example, polysilicon. Further, an insulator 220 is arranged in the passage 205. In an embodiment, the inner diameter of the passage 205 can be, for example, sub-300 nm and the periphery of the sensor 100 can be approximately 1 pm.

[0024] In an embodiment the gate dielectric can be aluminum oxide (AI2O3), which can be used for sensing hydrogen, oxygen, and/or nitrogen oxide. The particular material of the gate dielectric can be different depending upon the particular molecules that are being sensed. For example, if the sensor 100 is a pH sensor, then the gate dielectric 210 can comprise hafnium oxide (FlfC>2). In other embodiments, the gate dielectric 210 can include an enzyme selected for the particular type of sensing. For example, if the sensor is designed to detect penicillin, then the gate dielectric can be, for example, an aluminum oxide (AI2O3) that includes the enzyme penicillinase.

[0025] As will be appreciated from Figures 1 , 2A and 2B, the cylindrical shape of the sensor 100 is particularly advantageous because it consumes less area than polyhedral-shaped sensors, such as lateral nanowire and two-dimensional atomic crystal sensors. Specifically, a nanotube device takes up d ² (d = diameter).

However, if the nanotube is cut along its length to use it as a 2D sheet of atomic thin film channel then it will use l x dx 3.14. Because one expects to use high aspect ratio nanowire or nanotube, the two-dimensional version of the same geography will require more area for its positioning. From a chip-area perspective, consider an array of vertically stacked gate all-around nanowire field effect transistor (GAA NWFET) having a minimum contact-gate pitch z of 5 nm, minimum device-device pitch l between 70 and 80 nm, and minimum contact width W of 20 nm for a pMOS device at the 15 nm technology node. Theoretically, 13 nanowires need to be stacked in the gate-all-around fashion to achieve a drive current of a single silicon nanotube FET having an inner core gate diameter of 100 nm. In order to compare one silicon nanotube FET with 13 x GAA NWFETs, consider that both devices have a back-gated source contact. For relaxed processing constraints, a contact width W of 300 nm is considered. The total contact area per unit length consumed by 13 nanowires based on the 15 nm technology node parameters is:

^A NW_norm = 13 X (l + z + 2 x W) ~ 8. 775 pm (1 ) [0026] The equivalent normalized contact area consumed by a silicon nanotube transistor can be calculated as:

A _NT _„ _o rm = 1 X (l + z + 3 x W) ~ 0. 975 mi ^h (2)

[0027] Taking the ratio of the two normalized contact areas gives a value of approximately 1 1 % (0.975 pm/ 8.775 pm). Thus, a single 20 nm gate length, 10 nm thick p-FET silicon nanotube transistor is capable of providing the output drive current of approximately 13 nanowires (20 nm diameter) in a gate-all-around configuration while maintaining an off-state leakage current similar to that of a single 20 nm diameter nanowire FET. At the same time the nanotube FET occupies a contact area equivalent to just around 1 1 % of that occupied by the 13 GAA

NWFETs.

[0028] To compare the nanotube FET with a lateral array of GAA NWFETs, one needs to consider the effective area footprint occupied by the 13 nanowires and a single nanotube. In the case of laterally stacked GAA NWFETs, if one assumes a nanowire pitch l of 4 nm and nanowire physical length L _Phys of 800 nm and diameters DNW of 20 nm, the total area occupied by 13 nanowires in the lateral array is approximately:

[0029] For the case of a single nanotube:

ANT norm = p x rf = 0. 038 pm ² (4) [0030] The total non-normalized area occupied by the nanotube is about 0.038 pm ² with the dimensions above. A ratio of the areas indicates that a single nanotube occupies an area of 15% compared to 13 (800 nm long) laterally stacked GAA nanowires.

[0031] Figure 2C illustrates a sensor system according to embodiments. As illustrated, the sensor system 200 includes a processor 225 coupled to the sensor 100 illustrated and described above in connection with Figures 1 , 2A, and 2B.

Specifically, the processor is electrically coupled to the source contact 120, the drain contact 125, and the gate contact 130. The processor 225 can obtain

measurements made by sensor 100. The processor 225 can be coupled to a display for outputting the measurements made by sensor 100. Alternatively, or additionally, the processor can include an integrated wired or wireless communication interface (or can be coupled to an external wired or wireless communication interface) to send the measurements made by sensor 100 to another device. The processor 225 can be any type of processor, such as, for example, a microprocessor, an application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like.

[0032] A method for forming the sensor 100 will now be described in connection with the flowchart of Figure 3 and the diagrams in Figures 4A-4K.

Initially, a nanotube structure 1 10 is formed on top of a substrate 105 (step 305). Specifically, as illustrated in Figures 4A-4C, a first doped layer 1 10A is formed on the substrate as the bottom portion of the nanotube structure 1 10, a second doped layer 1 10B is formed on top of the first doped layer 110A and serves as the middle portion of the nanotube structure 1 10, and a third doped layer 1 10C is formed on top of the second doped layer 1 10B and serves as a top portion of the nanotube structure 1 10.

[0033] As illustrated in Figure 4D, a drain contact 125 is then formed on top of the substrate 105 and is electrically coupled with a bottom portion of the nanotube structure 1 10 (step 310). More specifically, the drain contact is electrically coupled with the first doped layer 1 10A. A body 1 15 is formed on top of the substrate 105 so that it surrounds the nanotube structure 1 10 (step 315). Specifically, as illustrated in Figures 4E and 4F, first a gate dielectric 210 is formed around the periphery of the nanotube structure 1 10, and then a spacer 215 is arranged around the periphery of the gate dielectric 210. In an embodiment, the gate dielectric 210 can be, for example, aluminum oxide (AI2O3), hafnium oxide (Hf02), etc., and the spacer 215 can be, for example, polysilicon.

[0034] A gate contact 130 is then formed on top of the nanotube structure 1 10 so that the gate contact 130 is electrically isolated from the top of the nanotube structure 1 10 and is electrically coupled with a middle portion 1 10B of the nanotube structure 1 10 (step 320). Specifically, referring to Figures 4G-4J, a passage 205 is formed in the top portion 1 10C of the nanotube structure 1 10 to expose the middle portion 1 10B of the nanotube structure 1 10. Then an insulator 220 is formed on the inner periphery of the passage 205, as illustrated in Figure 4H.

[0035] In order to form the source contact in the following step, an L-shaped spacer 405 is formed so that a portion is on top of the substrate and another portion runs vertically along an outer periphery of the spacer 215. The gate contact 130 is then formed on top of the nanotube structure 1 10, which is illustrated in Figure 4J. The gate contact 130 passes through the passage 205 so that it is in contact with the middle portion 1 10B of the nanotube structure 1 10. Finally, a source contact 120 is formed so that it is electrically coupled to a top of the nanotube structure 1 10 (step 325). As illustrated in Figure 4K, the source contact 120 is formed so that it is on top of the L-shaped spacer 405, a top portion of spacer 215 and gate dielectric 210, and the top of the nanotube structure 1 10.

[0036] Although the method of Figures 3A and 4A-4K has been described as forming the doped layers 1 10A-1 10C at the beginning of the process, these layers can be initially formed undoped and the doping can be performed after the body 120 is formed, for example, using vertical and angled ion implantation to form the source and drain.

[0037] As will be appreciated from the method described above, the formation of the sensor 100 is particularly advantageous because it does not require any type of transfer process, which allows the formation of a compact sensor with more precise positioning of components of the sensor.

[0038] The method described above in connection with Figures 3 and 4A-4K is a bottom-up method of forming a sensor. The sensor can also be formed using a top-down method, which will now be described in connection with Figures 5 and 6A- 6H. Initially, as illustrated in Figure 6A, a nanotube structure 610 is formed on a substrate 605 (step 505). An oxide layer 615 is then formed on top of the substrate 605 (step 510), which is illustrated in Figure 6B. As illustrated in Figure 6C, a gate dielectric layer 620 is formed on the oxide layer 615 and on a top portion and outer periphery of the nanotube structure 610 (step 515). A gate 625 is formed on top of the gate dielectric layer 620 (step 520), which is illustrated in Figure 6D.

[0039] The gate 625 is then patterned (step 525) and an oxide layer 630 is then formed on top of the patterned gate 625 and the oxide layer 615 (step 530).

The resulting structure is illustrated in Figure 6E. As illustrated in Figure 6F, portions of the gate 625 are removed to expose the drain region 640 (step 535).

[0040] The oxide layers 615 and 630 are removed (step 540), the nanotube structure 610 is then masked (step 545), and the source 645, channel 650, and drain 655 are formed (step 550). This is illustrated in Figure 6G. The formation of the source 645, channel 650, and drain 655 can be performed by, for example, implantation. As an alternative to forming the source 645, gate 650, and drain 655 at this stage in the processing, the source 645, gate 650, and drain 655 can be formed after the nanotube structure 610 is initially formed in step 505. Finally, as illustrated in Figure 6H, the source contact 660, inner gate contact 665, drain contact 670 and outer gate contact 675 are formed and an oxide protective layer 680 is formed (step 555).

[0041] The disclosed embodiments provide methods and electronic structures (e.g., sensors and sensor systems) that are very space-efficient and provide a large surface for sensing, thus increasing sensing response times, which are particularly appropriate for loT devices. It should be understood that this description is not intended to limit the invention. On the contrary, the exemplary embodiments are intended to cover alternatives, modifications and equivalents, which are included in the spirit and scope of the invention as defined by the appended claims. Further, in the detailed description of the exemplary embodiments, numerous specific details are set forth in order to provide a comprehensive understanding of the claimed invention. However, one skilled in the art would understand that various

embodiments may be practiced without such specific details.

[0042] Although the features and elements of the present embodiments are described in the embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the embodiments or in various combinations with or without other features and elements disclosed herein.

[0043] This written description uses examples of the subject matter disclosed to enable any person skilled in the art to practice the same, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the subject matter is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims.