FOR TRANSIMPEDANCE AMPLIFIERS

FIELD OF THE INVENTION

This invention relates to providing circuitry for controlling the amplification of an input signal, in particular for burst-mode input signals for use with Transimpedance Amplifiers.

BACKGROUND

Passive Optical Networks (PONs) may use Burst-Mode (BM) Transimpedance Amplifier (TIA) based Receivers within the upstream Optical Line Terminal (OLT) equipment present in the Central Office.

Circuitry may be used to control the amplification of an input signal into the OLT. Existing prior art circuitry may aim to achieve rapid settling of the amplified signal either by only having Automatic Gain Control (AGC), or sometimes having Automatic Offset Control (AOC) included, but the circuitry cannot deal with very high input overload levels.

Existing BM AGC/ AOC circuitry, such as the circuitry 100 shown in Figure 1, essentially relies upon a peak detector 102 feeding a stack of sampling comparators 103a, 103b with different thresholds 113a, 113b for detecting various signal levels at the output 109 of the TIA Front- End (FE) stage 101. The objective is to control the TIA FE’s 101 output signal 109 amplitude and offset so that distortion at its output 109 is minimized and thereby, distortion is minimized through the Back-End Signal-Path 107. There are many variations of this scheme, but they all rely on the same fundamental principle of using stacked comparators 103 a, 103b and a single sampling decision step.

The comparator outputs I l la, 111b may be latched, using latches 104a, 104b, to retain the sampling decisions which control the gain of the TIA FE 101. In some existing implementations, the comparators 103a, 103b may also control current sinking devices attached to the TIA FE 101 input node in order to remove the offset current from the input signal 108. The input signal may be received from a photodiode 106.

This stacked comparators 103a, 103b method may only work effectively when the input signal 108 offset is small enough so that the output 109 of the TIA FE 101 does not completely collapse to ground. If a large input offset does make the TIA FE 101 output 109 collapse to ground, then all output signal information may be lost and the output signal 109 is extremely unlikely to be recovered correctly with minimal distortion within a single sampling decision step.

The collapsing of the TIA FE 101 output voltage 109 at high input signal 108 offsets becomes a bigger problem as the TIA FE’s 101 power supply voltage is reduced and/or its feedback resistance 105 (Rf) is increased to achieve greater sensitivity. Therefore, the existing stacked comparators 103 a, 103b based scheme is not effective for use in low voltage, high sensitivity BM TIA 101 systems with large input overload signals 108.

Figure 2 shows an existing general prior art scheme for a unit cell (UC) 200 that may be used for the purposes of achieving BM AGC/AOC functionality. By means of a peak detector 201, each UC 200 samples the output signal amplitude (Vin) 204 of the TIA FE 101 and compares its (Vpeak) 206 to a reference voltage (Vref) 207 via a comparator 202. The output decision 208 of the comparator (Vcomp) 202 is stored in the digital latch 203. The latch may output the output signal (Out) 209 and its logical inverse (Out) 210. The reset signal 205 is inputted into each of the peak detector 201, the comparator 202 and the latch 203 individually.

It is desirable to develop improved BM AGC/AOC circuitry which may be used with low voltage and/or high sensitivity amplifiers 101 which may have large input overload signals 108.

SUMMARY

According to a first aspect, there is provided circuitry for controlling the amplification of an input signal, the circuitry comprising: an amplifier for receiving an input signal and being configured to amplify the input signal to generate an amplified signal; a cascading series of N comparison blocks, Ci, C2, ... C _n -i, C _n , ... CN, each comparison block, C _n , being for receiving a reset input signal from a previous comparison block, C _n -i, and being configured to receive the amplified signal; wherein each comparison block is further configured to control its state in dependence on the reset input signal and the amplified signal. The reset input signal that may be received by the first comparison block may be from a different source than a previous comparison block. In this way, the control of each comparison block, and consequently the control of the amplifier, may be dependent on the reset signal from the previous comparison block in the cascading series of comparison blocks.

In some implementations, the circuitry may be configured wherein each of the comparison blocks are configured to generate a respective output signal to be feedbacked in dependence on the amplified signal. In this way, the comparison blocks may provide the amplifier with one or more controller signals.

In some implementations, the circuitry may be configured wherein each of the comparison blocks are configured to: receive a reference signal; compare the amplified signal with the reference signal; and generate the respective output signal in dependence on the comparison between the amplified signal and the reference signal. In this way, the output signal may be based on the difference between the amplified signal and the reference signal.

In some implementations, the circuitry may be configured wherein the amplifier is further configured to control the amplification of the input signal in dependence on each of the output signals that are feedbacked. In this way, the amplification may be varied and controlled based on the feedback loop derived from the amplified signal.

In some implementations, the circuitry may be configured wherein each of the comparison blocks are configured to generate a reset output signal from the reset input signal, the reset output signal of a previous comparison block, C _n -i, being used as a reset input signal of the comparison block, C _n . In this way, the reset signals of the different comparison blocks may be interrelated with one another.

In some implementations, the circuitry may be configured wherein each comparison block is configured to adopt a reset state in response to receiving the reset input signal. In this way, the state of a comparison block, C _n , may be controlled based on the reset signal generated by a previous comparison block, C _n -i.

In some implementations, the circuitry may be configured wherein each comparison block is configured to remain in the reset state if the amplified signal amplitude is equal to or greater than the reference signal amplitude, in the reset state the output signal is not feedbacked to control the input signal. In this way, the reset state may be altered, or controlled based on the difference between the amplified signal and the reference signal.

In some implementations, the circuitry may be configured wherein the comparison blocks are configured to shift into a control mode if the amplified signal amplitude is less than the reference signal amplitude, in the control mode the output signal is feedbacked to control the input signal. In this way, the reset state may be altered, or controlled based on the difference between the amplified signal and the reference signal.

In some implementations, the circuitry may be configured wherein each comparison block is configured to remain in the reset state if the input signal amplitude is less than the reference signal amplitude, in the reset state the output signal is not feedbacked to control the input signal. In this way, the reset state may be altered, or controlled based on the difference between the amplified signal and the reference signal.

In some implementations, the circuitry may be configured wherein the comparison blocks are configured to shift into a control mode if the amplified signal amplitude is equal to or greater than the reference signal amplitude, in the control mode the output signal is feedbacked to control the input signal. In this way, the reset state may be altered, or controlled based on the difference between the amplified signal and the reference signal.

In some implementations, the circuitry may be configured wherein each comparison block is configured to receive the same reference signal.

In some implementations, the circuitry may be configured wherein each comparison block, C _n , is configured to receive a lower reference signal than the previous comparison block, C _n -i. In some implementations, the circuitry may be configured wherein each comparison block, C _n , is configured to receive a higher reference signal than the previous comparison block, Cn-1.

By varying the reference signal received by the comparison blocks, this may enable the control logic of the comparison blocks to be altered, which may in turn vary the decisions of the comparison blocks depending on the design requirements for the circuitry.

In some implementations, the circuitry may be configured wherein the circuitry comprises resistive feedback devices configured to receive each of the output signals that are feedbacked and control the amplification of the input signal in dependence on these output signals. In this way, the amplification of the input signal may be controlled by the resistance of the circuit path through the amplifier.

In some implementations, the circuitry may be configured wherein the resistive feedback devices are configured to control the amplification of the input signal by controlling the resistance in a circuit path parallel to the amplifier. In this way, the amplification of the input signal may be controlled by the resistance of the circuit path through the amplifier.

In some implementations, the circuitry may be configured wherein the circuitry comprises offset current devices configured to receive each of the output signals that are feedbacked and control the offset current of the input signal in dependence on the output signals.

In some implementations, the circuitry may be configured wherein the offset current devices are configured to control the offset current of the input signal by current sinking. In this way, the offset of the amplifier’s output signal following amplification of the input signal may be controlled by the offset current in the input signal.

In some implementations, the circuitry may be configured wherein the amplifier is a transimpedance amplifier.

In some implementations, the circuitry may be configured wherein the circuitry further comprises a photodiode configured to receive an optical input and convert the optical input into the input signal, the input signal being an electrical signal. In this way, the optical signals from outside of the circuitry may be converted into an electrical signal which may be processed by the circuitry.

In some implementations, the circuitry may be configured wherein the optical signal comprises burst and/or discrete data amplitudes.

According to a second aspect there is provided an optical line terminal comprising the circuitry of any preceding claim.

According to a third aspect there is provided a passive optical network comprising the optical line terminal above.

In some implementations, the passive optical network may be configured to comprise a postprocessing device interface configured to receive the amplified signal and generate a postprocessed amplified signal from the amplified signal.

In some implementations, the passive optical network may be configured to comprise a media access controller configured to receive the post-processed amplified signal and control access to the post-processed amplified signal.

In some implementations, the passive optical network may be configured wherein the postprocessing device interface and/or the media access controller is configured to generate the reset input signal.

BRIEF DESCRIPTION OF THE FIGURES

The present invention will now be described by way of example with reference to the following accompanying drawings.

Figure 1 shows circuitry for controlling the amplification of an input signal of the prior art.

Figure 2 shows a prior art unit cell for the circuitry for controlling the amplification of an input signal. Figure 3 shows a passive optical network architecture including circuitry for controlling the amplification of an input signal.

Figure 4 shows circuitry for controlling the amplification of an input signal of an exemplary embodiment.

Figure 5 shows a plot of the simulated settled output amplified signal amplitude and offset versus the input signal for the circuitry of the exemplary embodiment.

Figure 6 shows a plot of the simulated transient output amplified signal amplitude and offset versus time for the circuitry of the exemplary embodiment.

DETAILED DESCRIPTION

The circuitry described herein concerns controlling the application of an input signal, in particular for use within a passive optical network.

Embodiments of the present system may tackle one or more of the problems previously mentioned by each of the cascading series of comparison blocks being for receiving a reset input signal from a previous comparison block, and the state of the comparison block being controlled in dependence on the reset input signal and an amplified signal. In this way, the control of each comparison block, and consequently the control of the amplifier, may be dependent on the reset signal from the previous comparison block in the cascading series of comparison blocks.

Figure 3 shows a passive optical network (PON) system architecture 300. The PON 300 may comprise an Optical Line Terminal (OLT) 316 with an OLT transceiver 303. Downstream data 314a, 314b, 314c may be transmitted from the OLT 316 to a plurality of customer Optical Network Units (ONU) 301a, 301b, 301c. The downstream data 314a, 314b, 314c may comprise continuous-mode (CM) data. Upstream data 315a, 315b, 315c may be transmitted to the OLT 316. The upstream data 315a, 315b, 315c may comprise burst-mode (BM) data. The downstream data 314a, 314b, 314c and the upstream data 315a, 315b, 315c may be carried on different wavelengths along a single fiber through means of Wavelength Division Multiplexing (WDM) 304. Time Division Multiplexing (TDM) may also be employed in both directions of data transfer to interleave the data 313a, 313b, 313c corresponding to different ONUs 301a, 301b, 301c. In the downstream direction, an optical splitter 302, such as a l-to-64 optical splitter 302, may broadcast the CM data from the OLT 316 to each ONU 301a, 301b, 301c. Filters within the ONUs 301a, 301b, 301c may ensure that each ONU 301a, 301b, 301c receives the correct data packet and rejects all others.

ONUs 301a, 301b, 301c may each be at significantly different distances from the OLT 316. In some implementations, some ONUs 301a, 301b, 301c may be close and others could be many kilometres away. Consequently, due to fibre loss, the burst data amplitudes arriving at the OLT Receiver (Rx) 307 may vary noticeably. In addition, the overall amplitude level of all bursts 315a, 315b, 315c may be greatly diminished by the substantial loss of the splitter 302 and there can also be significant differences in splitter losses 302 between various ONUs 301a, 301b, 301c. Furthermore, Transmitter (Tx) launch powers for different ONUs 301a, 301b, 301c can vary significantly. The overall effect of such losses and variations is that some ONUs 301a, 301b, 301c may present very large overload signals to the OLT Receiver 307, whilst others may pose very small sensitivity-level signals in comparison. The ratio of overload to sensitivity signal levels can therefore be very high. The peak-to-peak signal may be superimposed on an average power level which depends on the Extinction Ratio (ER) of the ONU LASER source.

Along with WDM components 304, the OLT Optical Transceiver Module (OTM) 303 may house an amplifier 308, such as a BM Transimpedance Amplifier (TIA) 308, a Photodiode (PD) 309, a CM LASER Diode Driver (LDD) 306 and a LASER Diode (LD) 305. The systems following the amplifier 308, and preceding the LDD 306, may depend on several factors, such as the data rate and the characteristics of the optical devices.

In commonly deployed Limiting Systems, the BM TIA 308 is followed by a BM Limiter Amplifier (LA) and a BM Clock/Data Recovery (CDR) system. If there is significant channel dispersion, hence Inter-Symbol Interference (ISI) present due to the Optical Fibre and/or due to bandwidth limitations of the PD, the Rx Signal-Path is preferably highly linear so that BM Electronic Dispersion Compensation (EDC) techniques can be employed. An implementation of a Linear System could involve the use of an Avalanche PD (APD), followed by a Linear BM TIA 308 which drives an Analog-to-Digital Converter (ADC) feeding into a Digital Signal Processor (DSP) system incorporating BM EDC and BM CDR functions.

On the Transmitter side, Pre-Emphasis may be used to mitigate some of the limitations of LDs and thereby improve the mask margin. The Tx/Rx Pre/Post-Processing devices 310/311 may interface with a Media Access Controller (MAC) system 312.

Following application of a signal burst to the input of the amplifier 308, the objective is to rapidly force its output amplitude and offset to sit within specified ranges with minimum distortion. In addition to rapid settling time, the amplifier 308 must be able to handle very large input overload signals and meet sensitivity requirements at high data rates.

Figure 4 shows Sequential Burst-Mode Automatic Gain/Offset Control (AGOC) circuitry which aims to overcome the fundamental limitations of existing prior art stacked comparatorbased schemes.

The basic principle behind the AGOC architecture in Figure 4 is to sequentially sample the TIA FE output multiple times in order to eventually correctly recover its collapsed output signal when the input offset current is very large. The feedback control system may comprise N cascaded AGOC unit cells (UCs).

The circuitry 400 may provide part, or all, of an OLT 316, as shown in Figure 3. The OLT 316 may be part of a passive optical network 300, as shown in Figure 3.

Figure 4 shows circuitry for controlling the amplification of an input signal of an exemplary embodiment.

The circuitry 400 may be configured to receive an optical input from outside of the OLT 316, as shown in Figure 3. The optical input may comprise burst and/or discrete data amplitudes, as described herein with reference to Figure 3. The optical signal may be received by a photodiode (PD) 406. The PD 406 may convert the optical input into an input signal 408. The input signal 408 may be an electrical signal. The circuitry 400 may comprise an amplifier 401. The amplifier 401 may be a transimpedance amplifier. The amplifier 401 may be configured to receive, and may receive, an input signal 408. The input signal 408 may be received by the amplifier 401 from the PD 406. The amplifier 401 may be configured to amplify the input signal 408. The amplifier 401 may generate an amplified signal 409 by amplifying the input signal 408.

The circuitry 400 may comprise a cascading series ofN comparison blocks 403. In other words, the comparison blocks 403 may be arranged in series. In this way, a signal may be transferred from one comparison block to the next comparison block.

N may denote the number of comparison blocks 403 in the series. In the exemplary embodiment shown in Figure 4, there are three comparison blocks 403a, 403b, 403c. It may be appreciated that the number of comparison blocks 403 may be varied depending on the design requirements for the circuitry 400. It is preferable for there to be more than one comparison block 403.

The first comparison block 403a may be denoted by Ci. The second comparison block 403b may be denoted by C2. The n ^th comparison block 403c may be denoted by C _n . A previous comparison block 403 to the n ^th comparison block 403 may be denoted by C _n -i.

Each comparison block 403 may be configured to receive the amplified signal 409. The amplified signal 409 may be received from the amplifier 401. As shown in Figure 4, the same amplified signal 409 may be received by each of the comparison blocks 403. The amplified signal 409 may be provided through the parallel circuitry arrangement to each of the series of comparison blocks 403. In other words, the amplified signal 409 may be split and transferred to each of the comparison blocks 403.

Each comparison block 403 may be for receiving a reset input signal 412. The reset input signal 412 may be received from a previous comparison block C _n -i 403. Each of the comparison blocks 403 may be configured to generate a reset output signal 413. The reset output signal 413 may be generated from the reset input signal 412. It is preferable for each comparison block 403 to use the reset output signal 413 of a previous comparison block C _n -i 403 as a reset input signal 412. In this way, the reset input signal 412 may be transferred along the series of N comparison blocks 403.

The first comparison block Ci 403a may be configured to receive the first reset input signal 412 from a reset pulse generator 402. The reset pulse generator 402 may be internal or external to the circuitry 400. In other words, the first comparison block Ci 403a may be the only comparison block 403 to not receive the reset input signal 412 from a previous comparison block 403. This reset input signal 412 that is received by the first comparison block Ci 403a, may be denoted as the first reset input signal 412a.

In the exemplary embodiment shown in Figure 4, the first comparison block Ci 403a may be configured to receive the first reset input signal 412a. The first comparison block Ci 403a may be configured to generate a first reset output signal 413a from the first reset input signal 412a. The first reset output signal 413a may be used as a second reset input signal 412b. The second comparison block C2 403b may be configured to receive the second reset input signal 412b. The second comparison block C2 403b may be configured to generate a second reset output signal 413b. The second reset output signal 413b may be used as an n ^th reset input signal 412c. The n ^th comparison block C _n 403c may be configured to receive the n ^th reset input signal 412c. The n ^th comparison block C _n 403c may be configured to generate an n ^th reset output signal 413c.

Each of the comparison blocks 403 may be configured to generate a respective output signal 411. In other words, the first comparison block 403a may be configured to generate a first output signal 411a, the second comparison block 403b may be configured to generate a second output signal 411b, and the n ^th comparison block 403c may be configured to generate an n ^th output signal 411c.

The output signal 411 may be feedbacked to the amplifier 401. The output signal 411 may be directly feedbacked to the amplifier 401, i.e. not via any other components. Alternatively, the output signal 411 may not be directly feedbacked to the amplifier 401, i.e. via any other components. The output signal 411 may be generated in dependence on the amplified signal 409. In other words, the amplitude and/or offset of the amplified signal 409 may affect the generation of the output signal 411.

Each of the comparison blocks 403 may be configured to receive a reference signal 410. The reference signal 410 may be received from a store which may be internal or external to the circuitry 400.

Each of the comparison blocks 403 may be configured to receive the same reference signal 410. In other words, the reference signal 410 may comprise the same value of amplitude and/or offset. Alternatively, each comparison block C _n 403 may be configured to receive a lower reference signal 410 than the previous comparison block C _n -i. In other words, a first reference signal 410a may be higher than a second reference signal 410b, which may be higher than an n ^th reference signal 410c. Alternatively, each comparison block C _n 403 may be configured to receive a higher reference signal 410 than the previous comparison block C _n -i. In other words, the first reference signal 410a may be lower than the second reference signal 410b, which may be lower than the n ^th reference signal 410c.

Each of the comparison blocks 403 may be configured to compare the amplified signal 409 with a respective reference signal 410. In other words, as shown in Figure 4, the first comparison block 403a may be configured to compare the amplified signal 409 with the first reference signal 410a, the second comparison block 403b may be configured to compare the amplified signal 409 with the second reference signal 410b, and the n ^th comparison block 403c may be configured to compare the amplified signal 409 with the n ^th reference signal 410c.

Each of the comparison blocks 403 may be configured to generate the output signal 411 in dependence on the comparison between the amplified signal 409 and the reference signals 410. In other words, depending on whether the amplified signal 409 is higher or lower than the reference signal 410, the output signal 411 may be adjusted or generated differently. Additionally, or alternatively, depending on whether the amplified signal 409 is higher or lower than the reference signal 410, the output signal 411 may or may not be generated at all. Each of the comparison blocks 403 may be configured to control its state, i.e. the comparison blocks’ 403 own state, in dependence on the reset input signal 412 and the amplified signal 409. In other words, depending on the value of the reset input signal 412 and/or the amplified signal 409, the state of the comparison block 403 may be controlled.

Each of the comparison blocks 403 may be configured to adopt a reset state in response to receiving the reset input signal 412. In the reset state, the comparison block 403 may be configured to not feedback the output signal 411 to the amplifier 401. For example, in the reset state, the comparison block 403 may be configured to not generate the output signal 411, or alternatively, the comparison block 403 may be configured to generate the output signal 411, but not to feedback the output signal 411 to the amplifier 401.

In one exemplary embodiment, each comparison block 403 may be configured to remain in the reset state if the amplified signal 409 amplitude is equal to or greater than the reference signal 410 amplitude. Correspondingly, each comparison block 403 may be configured to shift into a control mode if the amplified signal 409 amplitude is less than the reference signal 410 amplitude.

In an alternative exemplary embodiment, each comparison block 403 may be configured to remain in the reset state if the amplified signal 409 amplitude is less than the reference signal

410 amplitude. Correspondingly, each comparison block 403 may be configured to shift into a control mode if the amplified signal 409 amplitude is equal to or greater than the reference signal 410 amplitude.

In the control state, the comparison block 403 may be configured to feedback the output signal

411 to the amplifier 401. For example, in the control state, the comparison block 403 may be configured to generate the output signal 411 and feedback the output signal 411 to the amplifier 401.

The internal workings of the comparison block 403 will now be described in more detail. The comparison blocks 403 may comprise a unit cell structure similar to that shown in Figure 2. By means of a peak detector 201, each comparison block 403 may sample the amplified signal amplitude (Vin) 204, 409 of the amplifier 401 and compare the peak value (Vpeak) 206 to a reference voltage (Vref) 207, 410 via a comparator 202. The output decision 208 of the comparator (Vcomp) 202 may be stored in the digital latch 203. The latch 203 may output the output signal (Out) 209, 411 and its logical inverse (Out), or reset output signal, 210, 413. The reset input signal 205, 412 may be inputted into each of the peak detector 201, the comparator 202 and the latch 203 individually.

When the reset input signal 205, 412 of a comparison block 403 is logic high (HI), then the logic block may be reset, which may force the latch 203 to Out = LO / Out = HI and Vcomp = LO. If the reset input signal 205, 412 subsequently falls to logic low (LO), then the comparison block 403 may no longer be in a reset mode and the latch 203 output state may be determined by the size of the detected signal peak (Vpeak) 206 relative to the reference voltage (Vref) 207, 410.

When a comparison block 403 is not in the reset state, if it detects that Vin < Vref, then the Vcomp and thereby the Out node voltages both become HI, whilst Out goes LO. Conversely, if the comparison block 403 detects that Vin > Vref, then the inverse logic states apply, hence the comparator 202 and latch 203 outputs may remain as in the reset mode. Vin < Vref occurs when the amplifier 401 output amplitude and/or offset voltage may be too large due to input overload current. Vin > Vref may occur when the amplifier 401 is either not stressed by input overload, or operation of the AGOC system has removed excess amplitude/offset induced by overload.

The amplifier 401 may be further configured to control the amplification of the input signal 408 in dependence on each of the output signals 411 that are feedbacked. As described herein, the output signals 411 may or may not be feedbacked to the amplifier 401 depending on the comparison between the amplified signal 409 and the reference signal 410. Hence, only the output signals 411 that are feedbacked may be used to control the amplification of the input signal 408.

The circuitry 400 may comprise resistive feedback devices 405. As shown in Figure 4, the resistive feedback devices 405 may be arranged in a circuit path parallel to the amplifier 401. The resistive feedback devices 405 may be configured to receive each of the output signals 411 that are feedbacked. The resistive feedback devices 405 may control the amplification of the input signal 408 in dependence on the output signals 411 that are feedbacked. In particular, the resistive feedback devices 405 may control the amplitude of the input signal 408 in dependence on the output signals 411 that are feedbacked. The resistive feedback devices 405 may be configured to control the amplification of the input signal 408 by controlling the resistance in the circuit path parallel to the amplifier 401. For example, the resistive feedback devices 405 may increase or decrease the resistance in the circuit path parallel to the amplifier 401 to increase or decrease the output signal amplitude 409 of the amplifier 401. By changing the resistance of the resistive feedback devices 405, this may allow the amplification of the input signal 408 to be controlled.

The circuitry 400 may comprise offset current devices 404. The offset current devices 404 may be included instead of, or an addition to, the resistive feedback devices 405. As shown in Figure 4, the offset current devices 404 may be arranged in a shunt circuit path with the amplifier 401.

The offset current devices 404 may be configured to receive each of the output signals 411 that are feedbacked. The offset current devices 404 may control the amplification of the input signal 408 in dependence on the output signals 411 that are feedbacked. In particular, the offset current devices 404 may control the offset current of the input signal 408 in dependence on the output signals 411 that are feedbacked. The offset current devices 404 may be configured to control the offset current of the input signal 408 by using current sinking.

The workings of the circuitry 401 will now be described in more detail. The digital logic output voltages (Outl ...OutN) 209, 411 of the comparison blocks 403 may control both the gainsetting devices in the amplifier 401 resistive feedback network 405 and the offset-eliminating current sinking devices 404 attached to its input node. The precise amount of amplitude and/or offset that must be removed by each comparison block 403 and the number (N) of comparison blocks 403 needed may depend on the input overload, settling time and acceptable output amplitude/offset requirements. It can therefore be appreciated that the number of comparison blocks 403 may vary depending on the design requirements for the circuitry 400. The inverted reset output signal 413 of a comparison block 403 may drive the reset input signal of the subsequent comparison block 403 in the feedback direction. Therefore, a driven comparison block 403 may only exit reset mode and start to detect the signal at its Vin node if the driving comparison block 403 has determined that Vin < Vref. In other words, the cascaded comparison blocks 403 may operate in a preceding decision-dependent manner. This sequentially staged signal detection process may only start when the reset input signal 412 of a first comparison block 403 is forced to logic low by the reset pulse signal, which can originate from inside the circuitry 400 or from an external source 402. The peak detector 201, comparator 202 and latch 203 within a comparison block 403 may all receive the same reset pulse signal or reset input signal 412.

All of the comparison blocks 403 in the system may be identical. Alternatively, the comparison blocks 403 they can be made different, if necessary. For example, the comparison blocks 403 may be made different with different peak detector time-constants. The reference voltages (Vrefl . . . VrefN) 410 can also be either all identical, or they can differ, depending on whatever is necessary to optimize performance.

The PON 300 may comprise a post-processing device interface 311. The post-processing interface 311 may be configured to receive the amplified signal 409 from the circuitry 400. The post-processing interface 311 may generate a post-processed amplified signal from the amplified signal 409.

The PON 300 may comprise a media access controller (MAC) 312. The MAC 312 may be configured to receive the amplified signal 409 from the circuitry 400 and/or the post-processed amplified signal from the post-processing interface 311. The MAC 312 may also control access to the post-processed amplified signal.

The post-processing interface 311 and/or MAC 312 may also be configured to generate the first reset input signal 412a that is received by the first comparison block Ci 403a. In this arrangement, the reset pulse generator 402 may be external to the circuitry 400. When implemented within a very high speed/sensitivity/overload BM TIA, the Sequential AGOC system, such as that shown in Figure 4, may enable fast settling of the output amplitude and offset to within specified ranges, with minimum distortion.

The circuitry 400 of the exemplary embodiment may help to meet the fast settling time and very high input overload signal requirements of PON OLT BM Receiver systems.

Figure 5 shows the simulated settled output amplified signal amplitude 501 and offset 502 versus the input signal for the circuitry of the exemplary embodiment. The non-monotonic behavior may occur because when each Sequential AGOC comparison block 403 activates, the offset may be over-compensated, then as the input signal is increased further, there may be under-compensation until the next comparison block 403 is activated. It can be seen that the settled output amplified signal amplitude 501 and offset 502 variations over the full input signal range are constrained within narrow bands.

Figure 6 shows the simulated transient output amplified signal amplitude and offset versus time for the circuitry of the exemplary embodiment.

Due to the sequential cascaded nature of the AGOC system, the transient output voltage amplitude/offset 601 exhibits unique signature multiple step changes as it converges to its final settled state, as shown in Figure 6. This Sequential AGOC system may produce very fast settling times of a few tens of nanoseconds.

The phrase "configured to" or “arranged to” followed by a term defining a condition or function is used herein to indicate that the object of the phrase is in a state in which it has that condition, or is able to perform that function, without that object being modified or further configured.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.