Title:
SERDES MODULE CLOCK NETWORK ARCHITECTURE
Document Type and Number:
WIPO Patent Application WO/2022/126891
Kind Code:
A1
Abstract:
A SerDes module clock network architecture, comprising a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. The frequency division branches are in one-to-one correspondence with the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.
Inventors:
XIANG SHENGWEN (CN)
LIU YING (CN)
LIU YING (CN)
Application Number:
PCT/CN2021/082543
Publication Date:
June 23, 2022
Filing Date:
March 24, 2021
Export Citation:
Assignee:
SHENZHEN PANGO MICROSYSTEMS CO LTD (CN)
International Classes:
H03L7/197
Foreign References:
| CN1655457A | 2005-08-17 | |||
| CN208922244U | 2019-05-31 | |||
| US20160105273A1 | 2016-04-14 | |||
| US20190215142A1 | 2019-07-11 |
Attorney, Agent or Firm:
SHENZHEN CHINA INNOVATION SOUTH INTELLECTUAL PROPERTY AGENCY CO., LTD. (CN)
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