SERIAL-TO-PARALLEL CONVERTER, AND DISPLAY DEVICE INCORPORATING THE SAME

WIPO Patent Application WO/2013/061565

A1

A serial-to-parallel converter which includes n input latching elements, INL1, INL2,... INLn, configured to sample n successive data of a serial input data stream, respectively; k intermediate latching elements, IL1, IL2,... ILk, configured to sample outputs of a first k input latching elements, INL1, INL2,... INLk, of the n input latching elements, respectively, after a first k data of the n successive data have been sampled by the first k input latching elements, and before a final data of the n successive data has been sampled by the nth input latching element, INLn, and n output latching elements, OL1, OL2,... OLn, configured to sample outputs of the k intermediate latching elements and a remaining (n-k) input latching elements, INLk+1,... INLn-1, INLn, of the n input latching elements, respectively, after the nth data of the n successive data has been sampled by the nth input latching element, INLn, and before the kth data of a next n successive data in the serial input data stream has been sampled by the kth input latching element, INLk, wherein the n input latching elements and the k intermediate latching elements are transparent for one state of their clock input, and n and k are positive integers, where n>k.

JOHN GARETH
ZEBEDEE PATRICK

PCT/JP2012/006750

May 02, 2013

October 22, 2012

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SHARP KK (JP)
JOHN GARETH
ZEBEDEE PATRICK

H03M9/00

WO2009130989A1	2009-10-29
WO2009028353A1	2009-03-05

JP2000244330A	2000-09-08
JPH0520887A	1993-01-29
JPH05257640A	1993-10-08
JPH0438017A	1992-02-07

HARAKENZO WORLD PATENT & TRADEMARK (2-6 Tenjinbashi 2-chome Kita, Kita-ku, Osaka-sh, Osaka 41, JP)

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