Title:
SERIALIZER DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/119488
Kind Code:
A1
Abstract:
A serializer device 1 is provided with a first latch unit 11, a second latch unit 12, a conversion unit 13, a frequency division unit 14, a load signal generation unit 15, a phase difference detection unit 16, and a reset indication unit 17, making it possible to reduce a bit error rate early by a simple configuration. The phase difference detection unit 16 detects a phase difference between a first clock CLK1 applied to the first latch unit 11 and a third clock CLK3 applied to the second latch unit 12, and the reset indication unit 17 outputs a reset indication signal RSTn to the frequency division unit 14 when the phase difference is not within an intended range.
Inventors:
FUJITA YUSUKE (JP)
KUBO SHUNICHI (JP)
OSHIMA YOSHINOBU (JP)
KUBO SHUNICHI (JP)
OSHIMA YOSHINOBU (JP)
Application Number:
PCT/JP2017/000287
Publication Date:
July 13, 2017
Filing Date:
January 06, 2017
Export Citation:
Assignee:
THINE ELECTRONICS INC (JP)
International Classes:
H03K5/00; H04L7/00; H03K5/26; H03M9/00
Domestic Patent References:
| WO2004040835A1 | 2004-05-13 |
Foreign References:
| JPH06244739A | 1994-09-02 | |||
| JPH06104741A | 1994-04-15 | |||
| JP2009118449A | 2009-05-28 | |||
| JPH10107786A | 1998-04-24 |
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
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