FIELD OF THE INVENTION

The present invention relates generally to servo loop compensation techniques, and more particularly to a servo loop compensation technique that exhibits improved bandwidth and is especially useful in a disk, drive.

BACKGROUND OF THE INVENTION

The presently preferred embodiments of the invention relate to a servo loop compensation method and circuit especially useful in track following in a disk drive, and so the background of the invention will be discussed with reference to a disk drive. However, it should be noted that, except where they are expressly so limited, the claims at the end of this specification are not limited to applications involving disk drives.

A continuous closed loop control system may be configured as shown in FIGURE 1. In this example, a summing device 11 and controller circuit 100 are utilized to control a physical plant or process, which in this case is a magnetic recording system 15. In the system depicted in FIGURE 1, the controlled variable Y(t) is compared to a reference input X{t) . The reference input X(t) may be an electrical signal corresponding to a particular track on a disk, and the controlled signal may be a signal indicating the present position of a transducer with respect to the particular track or some other reference. The comparison between the reference input and the controlled variable

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occurs at the summing device 11, which could be a differential amplifier, multiplier, or some other signal processing circuit. The output of summing device 11 is an error signal E(t) that corresponds to the difference between the input X(t) and the output Y(t) . This error signal is provided as an input to the controller 100.

Controller 100 is a dynamic system added to the loop to stabilize and enhance the closed-loop system characteristics. The output of controller 100 is an actuating signal A(t) , which changes as a function of the error signal E(t) . The actuating signal A(t) is developed to correct the recording system 15, e.g., to control the position of a read/write (R/W) head over a desired track. The controller circuit 100 contains the control strategy for the entire servo control system. Within the control circuit 100 is a compensation component (s) . Typical compensation strategies utilize proportional, integral, and differential compensation techniques. The selection of the compensation components will greatly effect the response of the system. A typical goal of a controller is to position a read/write head over a given disk track as quickly as possible and to hold a transducer over the track as accurately as possible. The position of the read/write transducer is controlled by the servomechanism in accordance with signals from the read/write electronics of the system. Such control systems have been implemented as digital and analog systems. U.S. Patent No. 5,202,821, April 13, 1993, entitled "Sampled-Data Control System Exhibiting Reduced Phase Loss" , discloses further background relating to analog and digital control systems.

A primary goal of the present invention is to provide a track following servo-loop compensation technique with better loop bandwidth than that provided by conventional digital compensators. Improved bandwidth results in either (1) more accurate track following for a given number of servo samples on the disk, or (2) the same

performance with fewer servo samples, thereby permitting more of the disk surface to be used for data storage.

SUMMARY OF THE INVENTION

A servo controller is presented to generate an actuator output signal, A(t) , as a function of an input signal, E(t) , which is especially useful to control the read/write heads in a disk drive system. The servo controller of this invention has a proportional, an integral and a differential compensator portion. The proportional component produces a proportional output signal proportional to the input signal. The integral component produces an integral output signal as an integration of the input signal. The differential component produces a differential output signal as a differential of the input signal. Furthermore, the differential output signal is comprised of a first gain term summed with a second differential component having a second gain term in series with a constant delay. The actuator output signal is produced by a summation of the proportional output signal, the integral output signal and the derivative output signal.

In a presently preferred embodiment of this invention, the first and second gain terms are constants K _d and -K _d , respectively. Moreover, the differential component is a digital differentiator having a signal represented in the s-domain by the equation:

K _d (l-e ^~st« )

where t _d is a constant delay time.

According to a presently preferred embodiment, the entire compensator is implemented in a digital circuit. In another preferred embodiment of the present invention, the compensator is implemented as a combined digital and analog circuit. In the combined digital and analog embodiment, the analog circuit comprises a gain term. The analog gain term

comprises the proportional output signal and the differentiator gain term.

In a disk drive system, the present invention meets predetermined performance and reliability requirements using fewer, e.g., 60, servo samples per revolution on the disk. In contrast, a conventional digital controller would require 90 servo samples per disk revolution to achieve the same performance. Other features of the present invention are disclosed below.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and advantages of the invention will become more apparent and more readily appreciated from the following detailed description of the presently preferred exemplary embodiments of the invention taken in conjunction with the accompanying drawings, of which:

FIGURE 1 is a block diagram of a conventional servo system;

FIGURE IA is a block diagram of a prior art typical digital sampled-data control system employing an analog-to-digital converter as a sampling device and a digital-to-analog converter as a hold device;

FIGURE IB is a block diagram of the digital sampled-data control system of FIGURE IA in which the function of the an analog-to-digital converter has been replaced by an ideal sampler. The digital-to-analog converter has been replaced by an ideal zero-order-hold;

FIGURE IC is a block diagram of the digital sampled-data control system of FIGURE IB in which the function of the digital compensator has been illustrated as the sum of a proportional term, integral term, and differential term;

FIGURE ID is a block diagram of the combined digital and analog control system of a presently preferred embodiment of the present invention.

FIGURE 2A is a block diagram of the digital sampled-data control system that embodies aspects of the present invention;

FIGURE 2B is a block diagram of the digital sampled-data control system of FIGURE 2A in which the function of the proportional and integral blocks have been combined;

FIGURE 2C is a block diagram of a combined analog and digital control system which illustrates an alternative embodiment of the present invention where a constant gain analog path replaces the constant gain digital path of FIGURE 2B;

FIGURE 3A is an example of an error signal which may be applied to the control system of the present invention;

FIGURE 3B illustrates the output impulses produced by an ideal sampler in response to the error signal of FIGURE 3A;

FIGURE 3C illustrates the output signal of a constant gain (K _d ) block in response to the signal of FIGURE

3B.

FIGURE 3D illustrates the output signal produced by a zero-order-hold in response to the impulse train of FIGURE 3B; FIGURE 3E illustrates the output signal of the series combination of a constant gain (-K _d ) block and a pure time delay (t _d ) block in response to the signal of FIGURE 3B;

FIGURE 3F illustrates the output signal produced by a zero-order-hold in response to the impulse train of FIGURE 3E;

FIGURE 3G illustrates the sum of the signals of FIGURES 3D and 3F;

FIGURES 4A and 4B show the Bode plot comparing the conventional digital versus the digital differentiator employed within the control system of the present invention. FIGURE 4A illustrates the magnitude response, and FIGURE 4B illustrates the phase response;

1

- 6 -

FIGURES 5A and 5B show the Bode plot of the digital differentiator of the present invention for various time delays; and,

FIGURE 6 is a schematic of a preferred embodiment of the combined analog and digital embodiment of the present invention.

FIGURE 7 is a schematic diagram of the compensator circuit of the present invention employed in a disk drive servo loop.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A servo-loop controller according to the presently preferred embodiments will now be described with reference to the FIGURES. It will be appreciated by those of ordinary skill in the art that the description given herein with respect to those FIGURES is for exemplary purposes only and is not intended in any way to limit the scope of the invention. For example, the time periods used in data sampling are merely those which are presently preferred and are not intended to limit the invention. Moreover, example applications are used throughout the description wherein the present invention is employed in conjunction with a disk drive system. That disk drive system application is not intended to limit the invention, as the invention is equally applicable to other physical systems.

FIGURE IA is a block diagram of a conventional control system 10 wherein the controller 100 is implemented as a digital sampled-data system. Plant 15 is the physical system or process to be controlled. In one embodiment, for example, plant 15 might comprise a magnetic recording system, such as a disk drive system, in which the position of the transducer over the magnetic recording media is controlled by a servo mechanism that receives signals from the read/write electronics of the system. In such a case, the reference input, X(t) , represents the position for the track to be read from the media, and the controlled signal, Y(t) , represents the position of the transducer.

Sensing device 11 provides the comparison between the reference input, X(t) , and the controlled signal, Y(t) . The output of sensing device 11 is an error signal, E(t) , which corresponds to the difference between the reference input, X(t) , and the controlled signal, Y(t) . This error signal is provided as an input to the analog-to-digital converter 12.

As will be described more fully below, the controller in FIGURE IA is comprised of three major components an analog-to-digital converter 12, a digital compensator 13 and a digital-to-analog converter 14.

Analog-to-digital converter 12 receives the signal from sensing device 11 and outputs a digital number proportional to the error signal. The analog-to-digital converter 11 performs this conversion process once every sample period, T. This digital number is provided as an input to the digital compensator 13.

The digital compensator 13 physically may be a microprocessor which executes a software algorithm. This digital compensator 13 contains the control strategy and is added to the system to enhance the closed loop system characteristics. This combination of microprocessor and associated digital algorithm processes the input digital number from the analog-to-digital converter 12 and generates digital numbers which are provided as input to the digital- to-analog converter 14.

The digital-to-analog converter 14 receives the digital numbers from the digital compensator 13 and converts them to an electrical output signal which is provided as input to the plant 15. The output signal is an actuating signal, A(t) , which is developed for correction of the plant 15.

The plant 15 receives and responds to the actuating signal, A(t) , resulting in a change in the controlled signal, Y(t) . The resulting output, Y(t) , from the plant 15 is fed back to the sensing device 11 to close the loop.

FIGURE IB is a block diagram that illustrates how the physical system of FIGURE IA can be represented in order to mathematically model the control system. The analog-to- digital converter is replaced by an ideal sampler 16, and the digital-to-analog converter is replaced by an ideal zero-order-hold 17.

FIGURE IC is a block diagram which represents the digital compensator 13 as a sum of a proportional (P) 18, integral (I) 19, and differential (D) 20 blocks. This form of a control system is commonly referred to as a PID controller. The mathematical s-domain (Laplace) transfer functions (TF) of the proportional (P) 18, integral (I) 19, and differential (D) 20 blocks are given in equations (1)- (3) , respectively, as follows: TF _p (s) = K _p (1)

TF^s) = K, /(l-e ^sτ ) (2)

TF _d (s) = K _d (l-e ^sT ) (3)

As shown in FIGURE IC, the outputs of each of the respective blocks are summed by device 21 and this number is provided as an input to the zero-order-hold 17.

FIGURE ID is a block diagram of the digital control system of FIGURE IC in which the function of the zero-order-hold 17 has been depicted as three separate zero- order-holds associated with the proportional 18, integral 19 and differential 20 blocks. In this FIGURE, summing device 21 is depicted as adding the output of the zero-order-hold of each block. Importantly, such a system is mathematically equivalent to the system of FIGURE IC and has been depicted with separate zero-order-holds in order to more clearly describe the present invention.

An aspect of the present invention involves implementing the digital differentiator 20 part of the compensator 13 in a manner that reduces the phase loss of the controller 100 as compared with conventional controllers. Accordingly, the digital algorithm used to implement the digital differentiator 20 simulates the time domain sum of: 1) the sampled and held error signal and 2) ;

the delayed and inverted sampled and held error signal. FIGURE 2A is a block diagram m which the digital differentiator block 20 has been modified to represent the present invention. As can be seen, the new digital differentiator 20 is illustrated as the parallel combination of: 1) a constant gain block 22 and: 2) a constant gain block 23 in series with a constant delay block 24. Summing device 25 adds the result of the parallel paths. As will be described more fully below, the features of the present invention will become more apparent by tracing an exemplary error signal through the differentiator 20.

FIGURE 3A is an example of an analog error signal, E(t) 42, which may be applied to the controller 100 of the present invention. This signal represents the continuous difference between the reference signal, X(t) , and the controlled signal, Y(t) , i.e., the output from sensing device 11. When analog signal 42 is applied to the input of ideal sampler 16, the output of the sampler 16 is a train of impulses, each occurring at an integral multiple of the sampling period, T. This output, E ^* (t), is shown in FIGURE 3B, wherein the impulses are represented by arrows 43.

FIGURE 3C illustrates the output signal, K _d E ^* (t) 44, which is the pulse train 43 of FIGURE 3B multiplied by constant gain block 22, K _d . FIGURE 3D shows the output signal after the zero-order-hold associated with constant gain block 22. This signal 45 can be represented mathematically as K _d E ^* _h (t) , and illustrates the operation of the constant gain block 22, with its associated zero-order- hold, of the present invention as shown in FIGURE 2A. FIGURE 3E graphically depicts the operation of the constant gain block 23 in a series with a constant delay block 24. The resulting signal 46 represents the signal of FIGURE 3D inverted and delayed by a constant time, t _d . This signal 46 can be represented mathematically as -K _d E ^* (t-t _d ) . FIGURE 3F graphically depicts the operation of the output signal of FIGURE 3E after experiencing the effect of the sample-and-hold associated with constant delay block 24.

The resulting signal 47 can be represented mathematically as -K _d E ^* _h (t-t _d ) .

FIGURE 3G graphically depicts the operation of the summing device 25 in FIGURE 2A. The summing device 25 combines the output of the zero-order-hold associated with the constant gain block 22 with the output of the zero- order-hold associated with constant delay block 24. The resulting sum of signals 45 and 47 can be represented mathematically as K _d E ^* _h (t) - K _d E ^* _h (t-t _d ) and is graphically depicted as signal 48 in FIGURE 3G.

The transfer function of this digital differentiator can be expressed in the s-domain (Laplace) as :

rf _d (S)=K _d (l-e ^~std )

(4) Note that this is the transfer function of the output of this digital differentiator divided by the signal E ^* _h (t) . This transfer function does not include the effect of the zero-order-holds. This was done so that a direct comparison of the transfer function of a conventional digital differentiator (given by equation (3)) with the transfer function of the digital differentiator of the present invention (given by equation (4) ) can be clearly shown.

FIGURES 4A and 4B are Bode plots comparing the characteristics of the conventional digital differentiator (given by equation (3)) with the characteristics of the digital differentiator of the present invention (given by equation (4) ) . FIGURE 4A is a plot of the magnitude response of the two differentiators. The magnitude response of the differentiator of the present invention is shown by curve 50. The magnitude response of the conventional digital differentiator is shown by curve 51. FIGURE 4B is a plot of the phase response of the two differentiators. The phase response of the differentiator of the present

invention 52 shows a significantly reduced amount of phase loss compared to the phase response of the conventional digital differentiator 53. For illustrative purposes, a time delay, t _d , of 0.3T was used to generate these Bode plots.

As stated above, this delay time is typically limited to a minimum by the characteristics of the specific physical hardware (speed of the analog-to-digital converter, microprocessor, and digital-to-analog converter) used to implement the control system. The presently preferred digital embodiment can be implemented in a digital circuit as depicted in FIGURE IA wherein the digital compensator 13 is implemented using a microprocessor, and the compensator functions are implemented using a software program. Those skilled in the art should appreciate that a software program includes variations, such as a firmware implementation.

FIGURES 5A and 5B are Bode plots illustrating the response of the digital differentiator of this invention (given by equation (4) ) for various values of delay time, t _d . Curves 54a-57a of FIGURE 5A illustrate the magnitude, while curves 54b-57b of FIGURE 5B illustrate the phase characteristics of the digital differentiator of this invention with a delay time, t _d , of 0.1T, 0.3T, 0.5T, and 0.7T, respectively. Significantly, the response time of the system improves as the delay time decreases. Therefore, the response time of the system will be limited by the speed of the microprocessor in calculating the differential portion of the control system.

An alternative embodiment of the present invention is represented by the block diagram of FIGURE 2C. In the

FIGURE, the compensator circuit 13 is comprised of an analog and a digital portion. FIGURE 2B illustrates how the proportional and differential components of FIGURE 2A can be combined in block 26 such that the constant values of the differential control and the proportional control can be separated from the other portion of the compensator. Significantly, the constant gain path, K _d , of the

differentiator 22 and the proportional constant gain path 18 represented by K _p are combined m block 27 of FIGURE 2B Thus, as shown, the constant portion of the differentiator function is combined with the proportional constant. Now, since the block 27 is a constant gain block, it can be realized by an analog amplifier with a constant gain FIGURE 2C illustrates the final combined analog and digital embodiment The constant gam analog block 27 functions equivalently to the constant gain block 27 in FIGURE 2B This analog embodiment has the advantage of reducing the amount of calculation required in the digital algorithm and results in a small reduction in the overall phase loss of the system. The small reduction in phase loss is proportional to the calculation time saved in the digital compensator as a result of not having to do the calculations represented by the constant digital gain block 27. The amount of time saved is a function of the specific hardware used to implement the digital algorithm.

FIGURE 6 is a more detailed block diagram of a servo loop compensation circuit 100' in accordance with the combined digital and analog embodiment of the present invention. In this embodiment, the digital portion of the controller 100 comprises an A/D convertor 12, a digital integrator 19, a digital differential portion 124 that combines gam term 23 and constant delay 24, a summing term 33' and a D/A convertor 14. The analog portion includes a constant gam amplifier 27' providing a fixed gam of K _a , which is equivalent to K _d + K _p In addition, the servo loop controller circuit 100' includes another summing circuit (operational amplifier) 34' , and a power amplifier 160. The function of the block 124 is to implement the remaining portion of the differential algorithm (-K _d E(t-t _d )) in software or firmware in the microprocessor. The algorithm is as follows: l. read digitized position error from A/D

2 multiply this number by -K _d

3 output result to D/A

As noted above, the response time of combined digital and analog the system improves as the delay time decreases. Thus, the faster this algorithm is performed the better the system bandwidth. Figure 7 schematically depicts how the digital or the combined digital and analog compensator of the present invention can be employed in controller 100 used in connection with a recording system. A disk 60 comprising a plurality of prerecorded tracks 62 and sector servo signals 64 is read from or written to by a R/W head 66. The R/W head 66 is positioned by a servo motor 42 driven by an actuator circuit 70. A R/W circuit 72 communicates with the R/W head 66 via line 74.

The primary function of the system of FIGURE 7 is to accurately follow a particular track 62 on disk 60. The circuit of FIGURE 7 is best understood with additional reference to the servo models depicted in FIGURES 2A and 2C. The path of a track 62 on disk 60 in FIGURE 7 represent the signal X(t) depicted in FIGURES 2A and 2C. The absolute position of the R/W head 66 represents the signal Y(t) . In the instance of a perfectly circular track, the R/W head 66 could simply find the track centerline and remain fixed at that position. However, every track 62 deviates from a perfect circle and the head 66 must closely track those deviations. The difference between the position of R/W head 66 and the center of the track represents the error signal E(t) . Thus the summing (shown as 11 in FIGURES 2A and 2C) and the generation of the error signal occurs within the mechanical components of the disk drive of FIGURE 7 (i.e., the head in conjunction with the track) . The output via line 74 represents the signal E(t) .

In Figure 7, the relative position of the head with respect to the track is determined via the servo signals 64. Essentially, each servo signal 64 consists of an amplitude signal from two fields, A and B. The strength of the A field indicates head drift inward on the disk 60 and away from the track 62. On the other hand, the strength

of the B field indicates head drift outward on the disk 60 and away from the track 62. The relative amplitude of the A and B fields together represent the error signal E(t) . However, this error signal is in a format unusable by the controller 100. Thus, the R/W circuit 72 modulates the signal E(t) to a signal E' (t) , which is usable by the controller 100.

The controller circuit 100 receives the error signal E(t) and generates the actuating signal A(t) for use by the actuator circuit 70 to drive the head actuator 42 to position the R/W head 66 over the desired track. By employing the compensator circuit of the present invention, the servo-loop bandwidth is improved. .Improved bandwidth results in either (1) more accurate track following for a given number of servo samples on the disk, or (2) the same performance with fewer servo samples, e.g., the number of servo samples can be reduced to 60 while maintaining the performance of the track following. As a result of the fewer servo samples, more of the disk surface can be used for data storage.

Those skilled in the art will readily appreciate that many modifications to the invention are possible within the scope of the invention. For example, the techniques described herein are not limited to controlling disk drive systems. Other types of sampled-data control systems may utilize the techniques described such as robotic control systems, aircraft control systems and the like. Accordingly, the scope of the invention is not intended to be limited by the preferred embodiment described above but only by the appended claims.