Title:
SHEET FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT AND METHOD FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/175481
Kind Code:
A1
Abstract:
This sheet 1 for producing a three-dimensional integrated laminated circuit, which is interposed between a plurality of semiconductor chips having through-electrodes and is used to adhere the semiconductor chips to each other and obtain a three-dimensional integrated laminated circuit, is provided with at least a curable adhesive layer 13, wherein the adhesive layer 13 includes a thermally conductive filler and the standard deviation of the thickness (T2) of the adhesive layer 13 is 2.0 μm or less. This sheet 1 for producing a three-dimensional integrated laminated circuit can be used to produce a three-dimensional integrated laminated circuit having excellent heat dissipation properties.
Inventors:
NEZU YUSUKE (JP)
SUGINO TAKASHI (JP)
SUGINO TAKASHI (JP)
Application Number:
PCT/JP2017/005142
Publication Date:
October 12, 2017
Filing Date:
February 13, 2017
Export Citation:
Assignee:
LINTEC CORP (JP)
International Classes:
H01L21/60; C09J5/00; C09J7/20; C09J201/00; H01L21/301; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| WO2014069638A1 | 2014-05-08 |
Foreign References:
| JP2010010368A | 2010-01-14 | |||
| JP2012216837A | 2012-11-08 | |||
| JP2011063678A | 2011-03-31 | |||
| JP2011187571A | 2011-09-22 |
Attorney, Agent or Firm:
HAYAKAWA Yuzi et al. (JP)
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