Title:
SHEET FOR PROTECTING SURFACE OF SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER PROTECTION METHOD USING SHEET
Document Type and Number:
WIPO Patent Application WO/2011/152045
Kind Code:
A1
Abstract:
Disclosed is a semiconductor wafer surface protection sheet which has excellent adherence to the irregularities on the circuit formation surface of a semiconductor wafer, and has excellent detachability after being ground. Specifically, the semiconductor wafer surface protection sheet has: a substrate layer having a storage modulus (E) (25) at 25˚C of at least 1GPa; a resin layer (A) wherein the storage modulus (EA) (25) at 25˚C and the storage modulus (EA ) (60) at 60˚C satisfy the relationship EA (60)/EA (25) < 0.1, and the modulus of elongation (EA ) at 60˚C is 0.005-1MPa; and a resin layer (B) wherein the storage modulus (EB) (60) at 60˚C is at least 1MPa, and is greater than the storage modulus (EA) (60) at 60˚C of the abovementioned resin layer (A), and which has a thickness of at least 0.1μm but less than 100μm.
Inventors:
HAYASHISHITA, Eiji (())
林下 英司 (())
SAIMOTO, Yoshihisa (())
才本 芳久 (())
KATAOKA, Makoto (())
林下 英司 (())
SAIMOTO, Yoshihisa (())
才本 芳久 (())
KATAOKA, Makoto (())
Application Number:
JP2011/003063
Publication Date:
December 08, 2011
Filing Date:
May 31, 2011
Export Citation:
Assignee:
Mitsui Chemicals Tohcello, Inc. (Sumitomo Fudosan Kanda Bldg, 7 Kanda Mitoshiro-cho, Chiyoda-k, Tokyo 85, 〒1018485, JP)
三井化学東セロ株式会社 (〒85 東京都千代田区神田美土代町７ 住友不動産神田ビル Tokyo, 〒1018485, JP)
HAYASHISHITA, Eiji (())
林下 英司 (())
SAIMOTO, Yoshihisa (())
才本 芳久 (())
三井化学東セロ株式会社 (〒85 東京都千代田区神田美土代町７ 住友不動産神田ビル Tokyo, 〒1018485, JP)
HAYASHISHITA, Eiji (())
林下 英司 (())
SAIMOTO, Yoshihisa (())
才本 芳久 (())
International Classes:
H01L21/683; B24B1/00; B24B7/22
Attorney, Agent or Firm:
WASHIDA, Kimihito (8th Floor, Shinjuku First West Bldg.1-23-7, Nishi-Shinjuk, Shinjuku-ku Tokyo 23, 〒1600023, JP)
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Claims: