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Title:
SHIELDED CAPACITORS AND EMBEDDED MEMORY EMPLOYING SHIELDED CAPACITORS
Document Type and Number:
WIPO Patent Application WO/2019/132939
Kind Code:
A1
Abstract:
Memory devices in which a memory cell includes a select transistor and a capacitor (1T-1C) include a 2D array of metal-insulator-metal (MIM) capacitors. A conductive shield may separate adjacent capacitors. The conductive shield may be held at a reference potential, such as ground, and reduce disturbs between storage nodes of the array during memory device operation. Density of the MIM capacitors may be improved through the incorporation of the conductive shield where the shield geometry can be scaled through fabrication techniques. The capacitor array may occupy a footprint over a substrate. Transistors providing wordline and bitline access to the capacitor array may reside substantially within the capacitor array footprint, and when implemented with thin film transistors, the memory may be embedded within a logic device fabricated within a crystalline substrate substantially within the capacitor array footprint.

Inventors:
SHARMA, Abhishek A. (1091 NE Orenco Station Pkwy, Hillsboro, Oregon, 97124, US)
SUNG, Seung Hoon (2459 NW Parnell Terrace, Portland, Oregon, 97229, US)
RACHMADY, Willy (10945 SW Nutcracker Court, Beaverton, OR, 97007, US)
LE, Van H. (5625 NW Peregrine Pl, Portland, Oregon, 97229, US)
Application Number:
US2017/068799
Publication Date:
July 04, 2019
Filing Date:
December 28, 2017
Export Citation:
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Assignee:
INTEL CORPORATION (2200 Mission College Blvd, Santa Clara, CA, 95054, US)
International Classes:
H01L27/108; H01L49/02
Foreign References:
US20090001437A12009-01-01
US20040169217A12004-09-02
US6191442B12001-02-20
US20050059208A12005-03-17
US20030168717A12003-09-11
Attorney, Agent or Firm:
HOWARD, James M. (Green, Howard & Mughal, LLP,5 Centerpointe Dr. Suite 40, Lake Oswego Oregon, 97035, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1. An integrated circuit (IC) structure, comprising:

metal-insulator-metal (MIM) capacitor structures within vias, wherein the vias are in an interlayer dielectric (ILD) material, and individual ones of the MIM capacitor structures further comprise:

a first metal laterally adjacent to a sidewall of a via;

an insulator laterally adjacent to a sidewall of the first metal; and

a first portion of a second metal laterally adjacent to a sidewall of the insulator; and the IC structure further comprises one or more spacers over the ILD material, wherein: the one or more spacers comprise a dielectric material;

a second portion of the second metal is over the one or more spacers;

a third portion of the second metal is within a recess; and

the recess is in the ILD material between individual ones of the MIM capacitor

structures.

2. The IC structure of claim 1 further comprising a cap over the first metal, wherein the cap comprises a dielectric material, wherein the one or more spacers are laterally adjacent to a sidewall of the cap, wherein the second portion of the second metal is over the cap, and wherein the third portion of the second metal is laterally adjacent to a sidewall of the one or more spacers and laterally adjacent to a sidewall of the ILD material under the one or more spacers.

3. The IC structure of claim 1, wherein the via has a height within the ILD material, and wherein the third portion of the second metal is adjacent to the sidewall of the ILD material over at least 50% of the height.

4. The IC structure of claim 1, wherein:

individual ones of the one or more spacers completely enclose a circumference the via; and a lateral width of the third portion of the second metal adjacent to the sidewall of the one or more spacers is equal to a distance between the sidewall of a first of the spacers enclosing a first of the MIM capacitor structures, and a sidewall of a second of the one more spacers enclosing a second of the MIM capacitor structures, adjacent to the first of the MIM capacitor structures.

5. The IC structure of claim 4, wherein:

a lateral width of the one or more spacers is constant along a circumference of the via;

a distance between sidewalls of two of the one or more spacers enclosing adjacent ones of the MIM capacitor structures varies along the via circumference; and

the lateral width of the third portion of the second metal adjacent to the sidewall of the one or more spacers occupies the varying distance between the sidewalls.

6. The IC structure of claim 1 , wherein:

a lateral width of the third portion of the second metal adjacent to the sidewall of the one or more spacers is equal to a distance between an exterior sidewall of the first metal in adjacent ones of the MIM capacitor structures minus the lateral widths of the one or more spacers.

7. The IC structure of any one of claims 1-6, wherein the third portion of the second metal completely encloses individual ones of the MIM capacitor structures.

8. The IC structure of any one of claims 2-6, wherein, at least one of:

the one or more spacers and the ILD material have a different composition;

the cap and the ILD material have a different composition; or

the one or more spacers and the cap have a different composition.

9. The IC structure of any one of claims 1-6, wherein the second metal is electrically coupled to a reference voltage potential and wherein the first metal layer of individual ones of the MIM capacitor structures is electrically coupled to a first terminal of a select transistor.

10. The IC structure of any one of claims 1-6, wherein the second metal is electrically coupled to a reference voltage potential and wherein the first metal layer of individual ones of the MIM capacitor structures is electrically coupled to a first terminal of a select transistor comprising an amorphous or polycrystalline semiconductor material.

11. A computer platform including:

one or more processor; and

the IC structure of any one of claims 1-6, wherein the MIM capacitor structures are coupled to the processor.

12. An integrated circuit (IC) memory device, comprising:

peripheral circuitry comprising a plurality of field effect transistors (FETs), wherein

individual ones of the FETs comprise a monocrystalline semiconductor channel; and a memory cell array monolithically integrated with the peripheral circuitry, the array

comprising a plurality of metal-insulator-metal (MIM) capacitor structures coupled to a plurality of thin film transistors (TFTs), the TFTs further electrically coupled to wordlines extending in a row direction and bitlines extending in a column direction, orthogonal to the row direction, wherein individual ones of the TFTs employ a polycrystalline or amorphous semiconductor channel, and wherein individual ones of the MIM capacitor structures further comprise:

a first metal laterally adjacent to a sidewall of a via, the via in an interlayer dielectric (ILD) material;

an insulator laterally adjacent to a sidewall of the first metal; and a first portion of a second metal laterally adjacent to a sidewall of the

insulator; and

the memory cell array comprising one or more spacers over the ILD material, wherein: the one or more spacers comprise a dielectric material;

a second portion of the second metal is over the one or more spacers;

a third portion of the second metal is within a recess; and

the recess is in the ILD material between individual ones of the MIM capacitor structures.

13. The memory device of claim 12, wherein:

the capacitor structures have first terminals comprising the first metal, the first terminals of individual ones of the capacitor structures electrically coupled to first semiconductor terminals of individual ones of the TFTs;

the third portion of the second metal is laterally adjacent to a sidewall of the one or more spacers and laterally adjacent to a sidewall of a portion of the ILD material under the one or more spacers; and the via has a height within the ILD material, and wherein the third portion of the second metal is adjacent to a sidewall of the ILD material over at least 50% of the height.

14. The memory device of claim 12, wherein:

the one or more spacers completely enclose a circumference of the via; and

a lateral width of the third portion of the second metal adjacent to the sidewall of the one or more spacers is equal to a distance between sidewalls of two of the one or more spacers that enclose adjacent ones of the MIM capacitor structures.

15. A method of fabricating an integrated circuit (IC), the method comprising:

depositing a backbone layer over an interlayer dielectric (ILD) material;

forming a plurality of openings in the backbone layer;

forming one or more spacers along an interior sidewall of individual ones of the openings; forming vias into the ILD material not protected by either the backbone layer or the one or more spacers;

removing the backbone layer selectively to the one or more spacers;

forming one or more recesses into the ILD material not protected by the one or more spacers; forming a metal-insulator- metal (MIM) capacitor structure within the vias; and

forming a shield structure within the recesses.

16. The method of claim 15, wherein forming the MIM capacitor structure further comprises: depositing a first metal on a sidewall of the vias;

depositing an insulator on a sidewall of the first metal; and

depositing a second metal on a sidewall of the insulator.

17. The method of claim 16, wherein forming the shield structure further comprises

depositing the second metal within the recesses.

18. The method of claim 16, further comprising:

backfilling at least a portion of the vias with a sacrificial material;

planarizing the scarification material with a surface of first metal and a surface of the one or more spacers;

recessing the surface of the first metal below the surface of the one or more spacers; and forming a cap over the recessed surface of the first metal.

19. The method of claim 18, wherein the cap comprises a dielectric material, and wherein forming the shield structure further comprises depositing the second metal over the cap, over the spacers, and within the trenches.

20. The method of claim 18, wherein:

backfilling at least a portion of the vias with sacrificial material further comprises depositing the sacrificial material over the insulator before the second metal is deposited; and forming the trenches into the ILD material concurrently removes at least some of the

sacrificial material from the vias.

21. The method of claim 15, wherein:

removing the mask layer selectively to the spacers exposes a portion of the ILD material between spacers enclosing adjacent ones of the vias; and

forming the trenches into the ILD material comprising etching the ILD material between a first of the spacers enclosing a first of the vias, and a second of the spacers enclosing a second of the vias.

22. The method of claim 15, wherein forming the spacers further comprises depositing a layer of dielectric material having a different composition than the mask layer, and anistropically etching the layer of dielectric material selectively to the mask layer.

23. The method of any one of claims 15-22, wherein, at least one of:

the spacers and the ILD material have a different composition;

the cap and the ILD material have a different composition; or

the spacers and the cap have a different composition.

24. The method of any one of claims 15-22, wherein the first metal layer of individual ones of the MIM capacitor structures is electrically coupled through a bottom of the vias to a first terminal of a select transistor.

25. The method of any one of claim 15-22, further comprising:

forming a plurality of select transistors, the select transistors further comprising an

amorphous or polycrystalline channel semiconductor; and forming a peripheral circuit, wherein forming the peripheral circuit further comprises forming a plurality of field effect transistor (FET) structures.

Description:
Shielded Capacitors and Embedded Memory Employing Shielded Capacitors

BACKGROUND

Embedded memory may be integrated with a host IC as a multi-chip module (MCM) or may be monolithically integrated with a host IC (i.e., both memory and the host IC fabricated on the same chip). One form of embedded memory is embedded dynamic random access memory (eDRAM). The architecture of eDRAM is based on a 1T-1C cell that includes a“write” or“select” transistor and a storage capacitor. eDRAM may be integrated with a host microprocessor chip (such as a central processing unit or“CPU”) at the package level, for example, to form an central processor MCM. Integration of both a memory device and a processor proximate to one another in a same package may, for example, enable

communication between the memory device and the processor through a local bus capable of higher bandwidths and/or lower signal latencies relative to separately packaged chips communicating through a printed circuit board (PCB) bus.

For some eDRAM devices, a transistor of a memory cell is fabricated on and/or within a monocrystalline semiconductor during front-end-of-line (FEOL) processing. The capacitor may either be fabricated in the FEOL as well, or fabricated in the back-end-of-line (BEOL). A transistor and capacitor of each cell are electrically coupled through one or more metal interconnect layers formed in the BEOL. The BEOL is the portion of IC fabrication where individual semiconductor devices (whether embedded memory or logic transistors) are interconnected to one another through electrically conductive features such as metal interconnect traces (lines) within a given metallization level and metal-filled conductive vias between multiple metallization levels. These conductive interconnects are embedded in a dielectric material so that the memory device is a monolithic integrated circuit (IC).

An integrated circuit memory device suitable for eDRAM applications has a footprint occupying a chip area that is a function of at least the number of memory cells (i.e., total storage capacity of device), the memory cell density, and the layout of the device. Within each array, there may be a two-dimensional (2D) array of storage capacitors. Such a 2D capacitor array may be fabricated in the BEOL with each capacitor in the array implemented as a metal-insulator-metal (MIM) capacitor. Within each memory cell array, selection circuitry may be fabricated to allow addressing individual storage capacitors. Such selection circuitry may include a plurality of bitlines and a plurality of wordlines. Bitlines and wordlines are coupled to respective terminals of a selection transistor that is to pass or block electrical communication with the storage capacitors. The selection transistors may be fabricated as field effect transistors (FETs) employing a monocrystalline semiconductor device layer for at least the transistor channel, or fabricated as a thin film transistors (TFTs) employing a polycrystalline or amorphous semiconductor device layer for at least the transistor channel.

Typical peripheral circuitry of an IC memory device includes row circuitry that is electrically coupled to the wordlines, column circuitry that is electrically coupled to the bitlines, and control circuitry that is electrically coupled to the row and column circuitry.

Row circuitry may include, for example, wordline drivers. Column circuitry may include, for example, bitline sense amplifiers. Control circuitry may include, for example, logic to coordinate the functions of row circuitry and column circuitry. This peripheral circuitry is typically implemented with MOS technology employing FETs or TFTs that are fabricated concurrently with the select transistors.

For embedded memory applications, reducing the overall memory array footprint helps achieve larger memories and/or reduce device cost. One limitation of the memory array footprint is the density of the MIM capacitors. Scaling of a capacitor array can increase the occurrence of shorts between adjacent capacitors, for example resulting from misalignment of features during their fabrication. Even where fabrication techniques may permit further density increases, limitations on the operational voltages of an IC memory device may constrain the density of the MIM capacitors so as to avoid cross-bit cross-talk that induces errors in determining or setting the state stored in a cell.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example, and not by way of limitation, in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures: FIG. 1 illustrates a cross-sectional side view of a memory device structure including shielded capacitors, in accordance with some exemplary embodiments;

FIG. 2A illustrates an expanded cross-sectional view of the memory device structure shown in FIG. 1 that includes a portion of a capacitor array, in accordance with some exemplary embodiments;

FIG. 2B is a plan view of a capacitor array included in the memory device structure shown in FIG. 1, in accordance with some exemplary embodiments;

FIG. 2C is a plan view of a capacitor array included in the memory device structure shown in FIG. 1, in accordance with some other exemplary embodiments; FIG. 3 is a flow diagram illustrating methods for fabricating a capacitor array, in accordance with some embodiments;

FIG. 4 is a plan view of a capacitor backbone pattern suitable for the fabrication of shielded capacitors, in accordance with some exemplary embodiments;

FIG. 5, 6, 7, 8, 9, 10, 11, 12 and 13 are cross-sectional views illustrating a portion of a capacitor array evolving as selected operations in the method illustrated in FIG. 3 is practiced, in accordance with some exemplary embodiments;

FIG. 14 illustrates a mobile computing platform and a data server machine including a memory device with shielded capacitors, in accordance with some exemplary embodiments; and FIG. 15 is a functional block diagram of an electronic computing device, in accordance with some exemplary embodiments.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to“an embodiment” or“one embodiment” or“some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase“in an embodiment” or“in one embodiment” or“some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms“a”,“an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term“and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms“coupled” and“connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments,“connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other.“Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms“over,”“under,”“between,” and“on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material“on” a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term“at least one of’ or“one or more of’ can mean any combination of the listed terms. For example, the phrase“at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Memory devices comprising one or more arrays in which individual memory cells include a select transistor and a capacitor (IT- 1C) are described below. A 2D array of metal- insulator-metal (MIM) capacitors is coupled to a plurality of select transistors. An intervening conductive shield f may separate adjacent MIM capacitors associated with different memory cells. For some exemplary embodiments herein, the transistor of a IT- 1C storage cell is a TFT rather than a monocrystalline silicon-based transistor (e.g., MOSFET). Thin-film transistors (TFTs) are a class of field-effect transistors (FETs) in which the channel material is a deposited thin film rather than a monocrystalline material. TFTs have the advantage that the thin film deposition processes employed in TFT fabrication can be relatively low (e.g., below 450 °C), allowing TFTs to be inserted within layers of interconnect metallization of the type that is typically formed only after higher-temperature processing is completed in conventional silicon MOSFET fabrication technology. TFTs can employ semiconductor materials having various levels of long range order, including poly crystalline and amorphous. TFTs can also employ a wide variety of semiconductor materials, such as silicon, germanium, silicon-germanium, as well as various oxide semiconductors (a.k.a.

semiconducting oxides) including metal oxides like indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and the like.

TFT-based eDRAM embodiments described herein may advance MCM or monolithic integration of DRAM. Memory devices in accordance with embodiments herein may have any storage capacity (i.e., any number of bit cells) and one or more such memory device may be fabricated on a single IC chip. In some embodiments, for example, a memory device includes between 256 and 1024 wordlines and between 1024 and 4096 bitlines. For any memory device storage capacity, a memory device may have higher memory density and/or performance by introducing an intervening conductive (e.g., metal) shield between adjacent storage capacitors. As described further below, the intervening metal shield may implement a second capacitor sidewall that is common between two adjacent capacitors. The capacitors may therefore be considered at least partially double- walled. In some exemplary

embodiments, the intervening metal feature is conductively coupled to a first metal terminal of adjacent MIM capacitors. In some further embodiments, the intervening metal shield, along with the first metal terminal of adjacent MIM capacitors, is conductively coupled to a same reference potential (e.g., ground). The intervening metal shield may be functional as a shield between a second of the MIM capacitor plates for adjacent MIM capacitors. The intervening metal shield may thereby reduce parasitic across-capacitor (capacitive) coupling, which may improve memory cell state sensing margins and reduce noise in within a memory array. As described further below, an intervening metal shield may also be fabricated in a manner that reduces the likelihood of shorting within a MIM and between adjacent MIM capacitors relative to memory arrays lacking the intervening metal feature. These greater margins may facilitate further dimensional scaling to increase memory cell density while maintaining cell and array performance metrics. Although the addition of an intervening conductive shield to a memory array architecture may at first appear contrary to a goal of a high memory array density, a gain in memory density is possible where the introduction of intervening conductive shielding within the memory array enables adjacent capacitors to be more closely spaced without suffering the level of across-capacitor cross-talk that would occur to a greater extend absent the intervening conductive shield. Hence, where the intervening shield improves electrical isolation, and can be fabricated with lateral dimensions below that of a reference spacing, capacitor density can be increased.

FIG. 1 illustrates a cross-sectional side view of a memory device structure 100, in accordance with some exemplary embodiments. Memory device structure 100 includes an exemplary implementation of an intervening metal shield between adjacent capacitors. The cross-sectional view shown in FIG. 1 is along an A-A’ line that passes through capacitors coupled to one bitline of a memory array. Structure 100 further illustrates a portion of an IC that includes peripheral circuitry 180 over and/or on a substrate 101. Peripheral circuitry 180 includes a plurality of MOSFETs 181 that employ a monocrystalline semiconductor for at least the channel semiconductor 171. Peripheral circuitry 180 may further include one or more levels of interconnect metallization 105 embedded within interlayer dielectric (ILD) materials 103, 104. ILDs 103 and 103 ma may have any composition known to be suitable for electrical isolation of IC metallization, such as, but not limited to, materials including silicon and oxygen (SiO), materials including silicon and nitrogen (SiN), materials including silicon, oxygen, and nitrogen (SiON), low-k materials including a dopant (e.g., SiOF, SiOC), organosilicates, HSQ, MSQ, etc. In the exemplary embodiment illustrated, peripheral circuitry 180 includes metal-one (Ml), metal-two (M2) and metal-three (M3) interconnect metallization levels.

A plurality of TFTs 182 is located over peripheral circuitry 180. As shown, all TFTs 182 employ portions of semiconductor layer 102, which may be, for example, a continuous amorphous or polycrystalline film extending across, and/or between, TFTs 182. Memory cell 111A is denoted by dot-dashed line. Individual ones of TFTs 182 include a gate terminal (electrode) 135 separated from semiconductor layer 102 by a gate dielectric 120. In the exemplary embodiment illustrated, TFTs 182 are“top-gate” devices with gate terminal 135 being over semiconductor layer 302, however the architectures and techniques described herein however can also be implemented in any suitable“bottom-gate” devices. A dielectric spacer 130 separates a sidewall of gate terminal 135 from semiconductor terminal contact metallization 140, which lands on source and drain regions of semiconductor layer 102.

Contact metallization 140 backfills the region between adjacent dielectric spacers. Notably, with no bifurcation of semiconductor layer 302, TFTs 182 make a highly regular array that can be fabricated with only a few masks that establish initial grating patterns. Such 2D line patterns can be fabricated at nanometer dimensions (e.g., 10-20 nm features, or less). Self-aligned etch processes and/or damascene techniques, which are all highly scalable, may then be enlisted to generate TFTs 182 based on the initial grating pattern(s).

Memory cell 111A includes one storage capacitor of capacitor array 20. One capacitor terminal that includes metal 160 is electrically (e.g., conductively) coupled to a

semiconductor terminal (e.g., source) of a select transistor 15. Individual ones of storage capacitor array 20 are similarly coupled to a terminal of corresponding select transistors 15.

In the illustrative embodiment, each of the storage capacitors in array 20 has another terminal including a metal portion 161 connected in parallel through another metal portion 163 routed to a shared circuit node 25. During memory device operation, circuit node 25 may be maintained at a reference voltage potential (e.g., ground). Select transistors 15 have another semiconductor terminal (e.g., drain) electrically connected (e.g., conductively) to bitline metal 60. The gate terminal of select transistors 15 is connected to a respective wordline 10. Hence, memory cell 111A and the illustrated adjacent memory cells are electrically coupled to one bitline metal 60 with their respective select transistors 15 further coupled to separate wordlines 10. Memory cell 111A may be replicated over any given bitline length. Wordlines 10 may be connected to corresponding wordline drivers (or a similar voltage source) operable to bias the wordlines between a voltage sufficient to turn off a select transistor and a voltage sufficient to turn on a select transistor. For example, wordlines 10 may be coupled to a wordline driver operable to bias the wordline between a negative voltage (e.g., between 0V and -0.5V) sufficient to turn off an n-type transistor, and a positive voltage (e.g., between 0.5V and 2V) sufficient to turn on an n-type transistor.

In some exemplary embodiments illustrated by FIG. 3, bitline metal 60 comprises an interconnect metallization trace within a metallization level (e.g., M6) immediately above the metallization level (e.g., M5) in which TFTs 182 reside. In FIG. 3, bitline 60 is illustrated in dashed line as an indication that bitline 60 is behind the plane of the cross-sectional view illustrated. Hence, the bitline 60 metallization trace is what might be visible if a portion of dielectric 103 flush with the plane of the cross-section was milled out (e.g., with a FIB during a deprocessing). As further shown, via 148 provides electrical connection between bitline 60 and contact metallization landing on semiconductor terminals (e.g. drain semiconductor) of select transistors 15. Source terminals of select transistors 15 are electrically connected through local interconnect metallization 149. Local interconnect metallization 149 is within the same metallization level (e.g., M6) as bitline 60. Local interconnect metallization 149 is adjacent to, but electrically insulated, from bitline 60.

In further reference to FIG. 3, an individual local interconnect metallization 149 electrically interconnects a first MIM storage capacitor terminal including metal 160 with a semiconductor terminal (e.g., source) of select transistor 15. Capacitor metal portion 161 is separated from capacitor metal 160 by an intervening capacitor insulator 162. Capacitor insulator 162 may have any suitable relative permittivity (e.g., high-k such as HI ' CL, doped high-k material such as Al or Zr doped HIΌ2, etc.) as embodiments are not limited in this respect. In the exemplary embodiment shown, capacitor metal portion 161 is continuous with routing metal portion 163 across at least all capacitors 20 associated with bitline 60.

Capacitor metal portion 161 may also be continuous across capacitor array 20 associated multiple bitlines. Capacitor metal portion 161 may therefore tie one side of all capacitors of a memory array to a common plate reference potential through circuit node 25, implemented for example with another metallization level (e.g., M8).

In accordance with some embodiments, an intervening metal shield separates laterally adjacent MIM capacitors. In the example shown in FIG. 1, a shield metal portion 190 separates adjacent capacitors of capacitor array 20. Each shield metal portion 190 is in contact with routing metal portion 163 and therefore is electrically tied to capacitor metal portion 161. Hence, each shield metal portion 190 is tied to the same electrical potential as one terminal of all capacitors of a given bitline, or one terminal of all capacitors of multiple bitlines, or even one terminal of all capacitors of a memory array of an IC. As such, the second terminal of these capacitors is between a metal feature that can be tied to a common plate reference potential to improve shielding between adjacent storage capacitors.

Any number of interconnect metallization levels may be employed to route circuit nodes of the memory array to the underlying peripheral circuitry. In the example shown in FIG. 3, the capacitor reference potential at circuit node 25 is routed down through five metallization levels (e.g., M8-M3) to be in electrical communication with one or more control circuit employing FETs 181. Likewise, bitline 60 is routed down through three metallization levels (e.g., M6-M3) to be in electrical communication with one or more sense amplifier employing FETs 181. Wordlines 10 may also be routed down through one or more metallization levels (e.g., M4-M3) to be in electrical communication with one or more wordline driver employing FETs 181.

As noted above, select transistor 15 may be implemented as a TFT. While the memory device structures described herein are applicable to any thin film semiconductor material, including traditional group IV semiconductor materials such as silicon (Si), germanium (Ge), and SiGe alloys, TFT performance depends on the composition of the semiconductor employed as the transistor channel material. In some exemplary embodiments, TFTs 182 employ an oxide semiconductor for at least the channel material. An oxide semiconductor is a semiconducting oxide, or a semiconductor comprising oxygen. For such embodiments, the wide band gap oxide channel material offers low leakage. Semiconducting properties vary with the oxide semiconductor composition and microstructure· An oxide semiconductor thin film can be amorphous (i.e., having no structural order), or

poly crystalline (e.g., having micro-scale to nano-scale crystal grains). Hence, in addition to enabling a memory array to move off a monocyrstalline substrate, oxide semiconductor TFT- based embodiments described herein may include select transistors with a lower off-state leakage that further enable a reduction in capacitor size and increase TFT density.

Examples of oxide semiconductors include metal oxides with a transition metal (e.g., IUPAC group 4-10) or post-transition metal (e.g., IUPAC groups 11-15). In advantageous embodiments, the metal oxide includes at least one of Mg, Cu, Zn, Sn, Ti, Ni, Ga, In, Sb, Sr, Cr, Co, V, or Mo. The metal oxides may be suboxides (A2O), monoxides (AO), binary oxides (AO2), ternary oxides (ABO3), and mixtures thereof. Semiconductor layer 102 may be a p- type, n-type, or intrinsic material. In exemplary embodiments, semiconductor layer 102 is n- type as a number of oxide semiconductors have been found to be capable of significant electron densities. Some oxide semiconductors have also been found to be capable of significant electron hole densities. Many oxide semiconductors have high defect density nearer the valence band, but display good n-type electrical properties. Some oxide semiconductors have high defect density in the conduction band, but display good p-type electrical properties. In some embodiments, semiconductor layer 102 comprises a tin oxide (SnO x ), such as Tin (IV) oxide, or Sn0 2 - In other embodiments, the tin oxide is Tin (II) oxide (SnO) or a mixture of SnO and Sn0 2 , where x may range between 1 and 2. While the range of x may be expanded, semiconducting properties may be lost (e.g., the material becomes a pure conductor if x is to low, and a pure insulator if x is too high). In some other embodiments, semiconductor layer 302 comprises a zinc oxide (ZnO x ), such as Zn(II) oxide, or ZnO. In other embodiments, the zinc oxide is zinc dioxide (Zn0 2 ) or a mixture of ZnO and Zn0 2 , where x may range between 1 and 2. In some other embodiments, semiconductor layer 102 comprises titanium oxide (TiO x ), or SnO x . Exemplary oxide semiconductors that may have suitable p-type conductivity include copper oxide (CuO x ). In some CuO x embodiments, semiconductor layer 102 is Cu(I) oxide, or Cu 2 0. In other embodiments, semiconductor layer 102 is Cu(II) oxide (CuO) or a mixture of CuO and Cu 2 0, where x may range between 0.5 and 1. Still other exemplary oxide semiconductor compositions include NiO x . Any dopants, such as Al, may also be added to any of these metal oxides, such as ZnO.

Semiconductor layer 102 or various portions thereof, may be intentionally doped, or not. Compared to intrinsic oxide semiconductor that is not intentionally doped, n-type and p- type oxide semiconductors may have a higher concentration of impurities, such as, but not limited to, one or more group III element, group V element, and/or elemental hydrogen (H), and/or oxygen vacancies. Dopant levels in semiconductor layer 102 may be selected to arrive at an optimal threshold voltage associated with gating the oxide semiconductor within the channel and/or for lowest bulk and/or junction resistance within the source/drain region. In some embodiments where semiconductor layer 102 comprises ZnO x , the dopants may include In and Ga. In some specific examples, semiconductor layer 102 is InGaOdZnOf , often referred to simply as IGZO.

As further illustrated in FIG. 1, FETs 181 include a gate terminal 170 separated from channel semiconductor 171 by a gate dielectric 172. Channel semiconductor 171 separates semiconductor terminals 174 (source semiconductor and drain semiconductor). Contact metallization 175 lands on semiconductor terminals 174 and is separated from gate terminal 170 by an intervening dielectric spacer 177. Any materials and techniques known to be suitable for fabricating FETs may be employed for forming FETs 181. FETs 181 may be planar or non-planar devices, for example. In some advantageous embodiments, FETS 181 are finFETs. One or more semiconductor materials may be employed in FETs 181. As one example, FETs 181 employ a surface layer of a substantially monocyrstalline substrate 101. Substrate 101 may be any material known to be suitable for the fabrication of MOSFET (CMOS) circuitry, such as, but not limited to, group IV materials (e.g., silicon, germanium, and SiGe). FIG. 2A illustrates an expanded cross-sectional view of the memory device structure 201 highlighted by dashed line in FIG. 1. Structure 201 includes a portion of capacitor array 20, and further illustrates shield metal portion 190, in accordance with some embodiments.

As shown, shield metal portion 190 has a height (e.g., z-dimension) HI that is approximately equal to the height of the capacitor metal portion 161. Height HI may however be greater than, or less than, the height of the capacitor metal portion 161 and/or greater than, or less than, the height of the capacitor metal 160, with electrical shielding being superior for greater height HI. The height HI may however be limited so as to avoid contact between shield metal portion 190 and any underlying metallization, such as local interconnect metallization 149.

As further illustrated in FIG. 2A, metal 160 is on, or is laterally adjacent to, a sidewall of ILD 103. In the illustrated example, a sidewall of metal 160 is in direct contact with a sidewall of ILD 103. Capacitor insulator 162 is likewise on, or laterally adjacent to, a sidewall of capacitor metal 160. In the illustrated example, a sidewall of capacitor insulator 162 is in direct contact with a sidewall of capacitor metal 160. Capacitor metal portion 161 is on, or is laterally adjacent to, a sidewall of capacitor insulator 162. In the illustrated example, a sidewall of metal 161 is in direct contact with a sidewall of capacitor insulator 162.

Capacitor insulator 162 therefore laterally separates a sidewall of capacitor metal portion 161 from a sidewall of capacitor metal 160. A top surface of capacitor metal 160 is further separated from an overlying portion of routing metal portion 163 by a dielectric cap 210 that is over a top surface of capacitor metal 160. At their interface, dielectric cap 210 and capacitor metal 160 have substantially the same lateral dimension Wl. A sidewall of a portion of capacitor insulator 162 is also on, or laterally adjacent to, a sidewall of dielectric material 210. In the exemplary embodiment, dielectric cap 210 has a composition different from that of ILD 103. Dielectric cap 210 may have any composition known to be suitable for electrical isolation of IC metallization, such as, but not limited to, materials including silicon and oxygen (SiO), materials including silicon and nitrogen (SiN), materials including silicon, oxygen, and nitrogen (SiON), low-k materials including a dopant (e.g., SiOF, SiOC), organosilicates, HSQ, MSQ, etc. High-k materials (e.g., metal oxides) are also possible.

Routing metal portion 163 is also separated from ILD 103 by a dielectric spacer 215. Dielectric spacer 215 is over a top surface of ILD 103, and a sidewall of dielectric spacer 215 is on, or laterally adjacent to, a sidewall of dielectric cap 210. A sidewall of dielectric spacer 215 is also on, or adjacent to, a sidewall of shield metal portion 190. Dielectric spacer 215 therefore laterally separates a sidewall of dielectric cap 210 from a sidewall of capacitor metal 160. Over the height HI, dielectric spacer 215 and ILD 103 have substantially the same lateral dimension W2. In the exemplary embodiment, dielectric spacer 215 has a composition different from that of ILD 103 and different from that of dielectric cap 210. Dielectric spacer 215 may have any composition known to be suitable for electrical isolation of IC

metallization, such as, but not limited to, materials including silicon and oxygen (SiO), materials including silicon and nitrogen (SiN), materials including silicon, oxygen, and nitrogen (SiON), low-k materials including a dopant (e.g., SiOF, SiOC), organosilicates,

HSQ, MSQ, etc. High-k materials (e.g., metal oxides) are also possible.

FIG. 2B illustrates a top-down plan view of a MIM capacitor structure 205 that includes a portion of capacitor array 20, in accordance with some embodiments. The A-A’ line associated with the cross-sectional view in FIG. 2A is further shown in dashed line FIG. 2B. The view shown in FIG. 2B is through a plane of capacitor array 20 parallel to a plane of substrate 101 (FIG. 1) below routing metal portion 163, as demarked in FIG. 2A by the dashed B-B’ line. FIG. 2B illustrates an exemplary close-packed arrangement of cylindrical “via” storage capacitor structures. As shown, each storage capacitor comprises a plurality of annular layers with capacitor metal portion 161 being at the core of each storage capacitor.

As further shown in FIG. 2B, dielectric spacer 215 has an annular structure, an interior sidewall of which defines an outer (exterior) perimeter sidewall of a single storage capacitor via. An exterior sidewall of capacitor metal 160 lines an interior sidewall of dielectric material 103 that is underlying dielectric spacer 215 (as further shown in FIG. 2A). FIG. 2B also illustrates how dielectric cap 210 likewise has an annular structure as it lining the interior sidewall of dielectric spacer 215 in substantially the same manner as capacitor metal 160 follows the annular structure of dielectric material 103. An exterior perimeter sidewall of capacitor insulator 162 lines, or is on, or is adjacent to, an interior perimeter sidewall of capacitor metal 160. Capacitor insulator 162 therefore also has an annular structure. A portion of capacitor insulator 162 also lines an interior perimeter sidewall of dielectric cap 210. An exterior sidewall of capacitor metal portion 161 is on, or adjacent to, an interior perimeter sidewall of capacitor insulator 162. In the illustrated embodiment, capacitor metal portion 161 substantially fills the inner diameter of a via defined by capacitor insulator 162, but such fill may to be varying degrees, as denoted in FIG. 2A by divot 290. Shield metal portion 190 occupies the field surrounding the storage capacitors. Shield metal portion 190 is on, or laterally adjacent to the outer perimeter sidewall of dielectric spacer 215 and laterally adjacent to a perimeter sidewall of underlying ILD 103. Shield metal portion 190 may completely enclose dielectric spacer 215 of each storage capacitor, or may merely enclose groups of storage capacitors where dielectric spacer 215 merges as a result of close lateral proximity of the capacitors. In the exemplary embodiment illustrated in FIG. 2B, the annular structures of dielectric spacer 215 associated with two adjacent storage capacitors merges into a figure-eight including a merge point 295. The illustrated merging of dielectric spacer 215 may be advantageous for increasing the density of a capacitor array and may occur to varying degrees ranging from zero overlap between nearest neighbors to an arbitrary maximum overlap where shield metal portion 190 may be present over only a few degrees of arc between each storage capacitor. The degree of shielding achieved with shield metal portion 190 may therefore vary across a capacitor array as a function of localized variation in lateral separation between the capacitors of the array.

FIG. 2C illustrates a top-down plan view of a MIM capacitor structure 206 that includes a portion of capacitor array 20, in accordance with some alternative embodiments wherein routing metal portion 163 is discontinuous over the capacitor array. In this example, routing metal portion 163 has filled in trenches within an ILD that is over capacitor array 20. Routing metal portion 163 follows stripes (e.g., 202 and 203) denoted by dashed lines.

Within the footprint of the routing metal portion, shield metal portion 190 is present substantially as described above in the context of FIG. 2A and 2B. Outside of the footprint of routing metal strips 202 and 203, a backbone material 220 occupies the field surrounding the outer perimeter sidewall of dielectric spacer 215 (and the outer perimeter sidewall of underlying ILD 130). If fully sacrificial, backbone material 220 may have any composition ranging from a dielectric material, semiconductor (e.g., polysilicon, etc.), or metal (e.g., titanium, etc.). However, in embodiments where some portion of backbone material 220 may be retained, either by design, or as a result of process margins, electrical shorts within the capacitor array may be minimized where backbone material 220 is a dielectric material having any composition known to be suitable for electrical isolation of IC metallization. For example, backbone material 220 may be a dielectric such as, but not limited to, materials including silicon and oxygen (SiO), materials including silicon and nitrogen (SiN), materials including silicon, oxygen, and nitrogen (SiON), low-k materials including a dopant (e.g., SiOF, SiOC), organosilicates, HSQ, MSQ, etc. In an exemplary embodiment, backbone material 220 has a composition different from dielectric materials 103, 210 and 215. With the architecture shown in FIG. 2C, subsets of storage capacitors tied to different voltage potentials may have conductive capacitor shields that are electrically insulated from capacitor shields of adjacent storage capacitor subsets by the intervening backbone material 220.

With certain structural features of example memory devices now described, the fabrication of such devices is now described in further detail. FIG. 3 is a flow diagram illustrating methods 301 for fabricating a memory device, in accordance with some embodiments. Methods 301 begin at operation 605 where a substrate is received. The substrate received may advantageously include a monocrystalline semiconductor layer, such as a silicon layer, and may further include FETs, and may further include BEOL

metallization levels coupling the FETs include peripheral FET circuitry. In some examples, the substrate received at operation 305 includes both n-type and p-type FETs interconnected into a CMOS peripheral circuit. In some further embodiments, the substrate received includes TFTs within BEOL metallization levels over the FET circuitry. In some exemplary embodiments, TFTs are fabricated in a metallization level over the peripheral circuit. Hence, the substrate received at operation 305 may have been processed upstream of methods 301, for example to fabricate FETs and one or more levels of BEOL interconnect metallization over the FETs. Methods 301 then continue with fabrication of MIM capacitors in a f around the capacitor backbone structure. For capacitor backbone formation, any deposition process(es) known to be suitable for the desired composition and microstructure may be employed at operation 310. For example, any of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (CVD), e-beam deposition (EBD), or pulsed laser deposition (PLD) may be employed to deposit a thin film of backbone material. Following film deposition, the layer of backbone material may then be patterned, for example with any known lithographic mask patterning process(es) followed by any etch process(es) known to be suitable for the material composition. In some embodiments, for example, an anisotropic dry (plasma) etch is employed to pattern the capacitor backbone material into the capacitor backbone.

FIG. 4 is a top down plan view of an IC structure 405 that includes the starting substrate and a backbone material 220 comprising a dark field perforated with plurality of openings (e.g., via holes) 410 having a predetermined inner diameter D. Openings 410 expose the underlying substrate dielectric layer 103. Each opening 410 is dimensioned to contain one storage capacitor. As shown in Fig. 4, perimeter edges of opening 410 may intersect nearest neighbors. Following the patterning of the backbone structures, a dielectric spacer material is formed along a sidewall of the backbone material. Notably, merged openings 410 that may occur when perimeter edges of the closed form polygons are incomplete (e.g., as a result of fabrication tolerances) may be separated by the subsequently deposited spacer dielectric as long as merge lateral dimension M is less than approximately twice the lateral spacer dielectric width W2.

FIG. 5 is a cross-sectional view of IC structure 505 along the A-A’ line also illustrated in dashed line for IC structure 405 (FIG. 4). IC structure 505 illustrates the addition of dielectric spacer 215 to IC structure 405. As shown in FIG. 5, dielectric spacer 215 is formed along a sidewall of backbone material 220. One or more of the materials described above for dielectric spacer 215 may be deposited as a blanket layer over backbone material 220 and over any exposed underlying substrate dielectric layer 103. Any deposition process(es) known to be suitable for the dielectric composition, such as any of those listed above (e.g., CVD), may be employed to deposit a spacer dielectric thin film. In some embodiments, the spacer dielectric thin film is deposited conformally with a thickness of the spacer dielectric along a sidewall of backbone material 220 being at least 80% the thickness of the spacer dielectric over a top of backbone material 220. Following deposition, the layer of spacer dielectric may then be patterned, for example with any anisotropic dry (plasma) spacer etch process(es) known to be suitable for the spacer dielectric composition, to arrive at the structure 505. Notably, dielectric spacer 215 is self-aligned to a sidewall of backbone material 220 with no lithographic patterning required to generate IC structure 505 from IC structure 405. In further view of the backbone polygons shown in FIG. 4, a continuous dielectric spacer 215 is formed within the interior of each of the closed form polygons defined by the backbone. Each of the openings of diameter D illustrated in FIG. 4A will therefore be lined with an annulus of dielectric spacer 215 of width W2. Optionally, two or more spacers (e.g., having different compositions) may be formed in substantially the same manner as described above for spacer 215 without departing from the scope and spirit of the teachings herein.

Returning to FIG. 3, methods 301 continue at operation 315 where a capacitor recess or“via” is etched into one or more layer of the substrate underlying the capacitor backbone. The capacitor backbone, as supplemented by dielectric spacer 215 therefore defines a mask for the capacitor via etch of operation 315. Operation 715 may entail any etch process suitable for the composition of the underlying layer. In the example embodiment further illustrated in FIG. 6, an anisotropic dielectric etch process is employed to form capacitor via 610 into ILD 103. IC structure 601 illustrated in FIG. 5 therefore includes IC structure 501 with the addition of capacitor recesses or vias 610. As shown, the capacitor via etch is masked by both dielectric spacer 215 and backbone material 220. The capacitor via etch is advantageously selective to ILD 103 (i.e., etches the composition of ILD 103 at a rate faster than that of dielectric spacer 215 and backbone material 220). As further shown in FIG. 6, both dielectric spacer 215 and backbone material 220 survive the capacitor via etch although their respective thicknesses have been reduced by the via etch. The capacitor vias 610 have a sidewall that is self-aligned to an interior sidewall of dielectric spacer 215. The capacitor vias 610 are etched to a height of H2 to expose or“land” on underlying local metallization 149. Capacitor vias 610 may have any sidewall slope or profile, typically having a mid-height diameter D1 that is somewhat larger than a bottom diameter D2. Although illustrated as a step function for simplicity, it is noted that the via diameter may vary continuously along the via height HI.

Returning to FIG. 3, methods 301 continue at operation 320 where the capacitor via is lined with a capacitor metal and capacitor dielectric. These materials do not completely fill the capacitor via. Rather than depositing another capacitor metal at this point in the fabrication process, a sacrificial backfill dielectric is instead deposited over the capacitor dielectric to fill any remaining recess within each capacitor via. In the example further illustrated in FIG. 7, IC structure 701 includes IC structure 601 with capacitor metal 160 having been deposited over the sidewall of ILD 103 within the capacitor vias 610. Capacitor metal 160 may be deposited with any technique (e.g., ALD, PVD, electrolytic plating, electroless plating) and to any thickness known to be suitable for the application as embodiments herein are not limited in this respect. As shown, capacitor metal 160 contacts underlying local interconnect metallization 149. Capacitor insulator 162 has been deposited over capacitor metal 160, contacting the sidewall of capacitor metal 160 within the capacitor vias 610. Capacitor insulator 162 may be deposited with any technique (e.g., ALD, CVD, etc.) and to any thickness known to be suitable for the application as embodiments herein are not limited in this respect. As shown, capacitor insulator 162 and capacitor metal 160 form continuous films that span multiple capacitor vias 610. Backfill material 710 has further been deposited over capacitor insulator 162, contacting the sidewall of capacitor insulator 162 within the capacitor vias 610. Backfill material 710 may be deposited with any technique known to be suitable for the application as embodiments herein are not limited in this respect. In some exemplary embodiments, backfill material 710 is dielectric, such as a flowable oxide, which may be deposited with a spin-on process, or with another deposition technique (e.g., PECVD). In some advantageous embodiments, backfill material 710 has the same composition as ILD 103.

Returning to FIG.3, methods 301 continue at operation 325 where the capacitor metal deposited at operation 320 is planarized with the surrounding dielectric material and then selectively recessed to a level below the surround dielectric material. The planarization process may remove overburden associated with each of the backfill dielectric, capacitor dielectric and capacitor metal that were deposited at operation 320. Any planarization process, such as chemical-mechanical planarization (CMP), may be employed to re-expose top surfaces of the dielectric spacer and capacitor backbone. Following planarization, the top surface of the capacitor metal is recessed with an etch process that is selective to the capacitor metal over at least one of the surrounding materials. In the example illustrated in FIG. 8, IC structure 801 includes IC structure 701 less the overburden associated with backfill material 710, capacitor insulator 162, and capacitor metal 160. A top surface of each of backfill material 710, capacitor insulator 162, and capacitor metal 160 are therefore planar with a top surface of and dielectric spacer 215 and backbone material 220. As further illustrated in FIG. 9, IC structure 901 includes IC structure 801 following a recess of capacitor metal 160. As shown, capacitor metal 160 has been recessed selectively relative to a backfill material 710, selectively to dielectric spacer 215 and selectively to backbone material 220. As such, recesses 910 are formed only over capacitor metal 160.

Returning to FIG. 3, methods 301 continue at operation 330 where a dielectric cap is deposited within the recesses formed at operation 325. The dielectric cap deposited at operation 330 is to electrically insulate (i.e., prevent shorts between) capacitor metals. The dielectric cap may be deposited with any suitable technique and is to be planarized to gap-fill the recess over the capacitor metal with a dielectric material that is planar with the surrounding materials. In the example further illustrated in FIG. 10, IC structure 1001 includes IC structure 901 with the addition of dielectric cap 210, which has been deposited into recesses 910 and planarized with the top surfaces of dielectric spacer 215, backbone material 220, and backfill material 710. At this point in the fabrication process, one or more top ILD layer (not depicted) may be optionally deposited over IC structure 1001, and then patterned to expose backfill material 710, capacitor insulator 162, and capacitor metal 160 with a bottom of capacitor metal routing trenches. Such operations may be performed, for example, to fabricate stripes of capacitor metal that separates the capacitor array into subsets of capacitors (e.g., as illustrated in FIG. 2C).

Returning to FIG. 3, methods 301 continue at operation 340 where the capacitor backbone is now removed anywhere that an overlying material does not protect the backbone. The capacitor backbone removal may be with any stripping process that is selective to the backbone material over the surrounding materials, particularly the dielectric spacer that is adjacent to the sidewall of the backbone material. Following backbone removal, the exposed ILD that is underlying the backbone is etched to form recesses that the metal shield features will ultimately occupy. In the example illustrated in FIG. 11 , IC structure 1101 includes IC structure 1001 less backbone material 220, which has been removed selectively to dielectric spacer 215 to form openings 1110 within which ILD 103 is exposed. In this example, backbone material 220 has been removed selectively to backfill material 710, capacitor insulator 162, and dielectric cap 210. FIG. 12 further illustrates an exemplary IC structure 1201 that includes IC structure 1101 following the etching of capacitor shield trenches 1220. Shield trenches 1220 are etched to a height of HI, for example with the same anisotropic etch process employed to form capacitor vias 610 (FIG. 6). In this exemplary embodiment where backfill material 710 has the same (or similar) composition as ILD 130, the shield trench etch removes backfill material 710 concurrently with the formation of shield trench 1220, thereby further forming capacitor recesses 1210 that expose capacitor insulator 162.

Returning to FIG. 3, methods 301 continue at operation 340 where the second capacitor metal is deposited into the capacitor recesses formed at operation 335. Any metal deposition process may be employed at operation 340. In some embodiments, the same metal deposition process employed at operation 320 is repeated at operation 340. Following metal deposition, any capacitor metal overburden may be further planarized with an ILD material overlying the capacitor array, if desired. The capacitor metal deposited at operation 340 is concurrently deposited within any previously formed shield recesses located between laterally adjacent capacitors. Methods 301 are then completed at operation 350 where any suitable IC processing may be performed to complete an IC. For example, one or more BEOL interconnect levels may be fabrication according to any suitable techniques. FIG. 13 further illustrates IC structure 201, substantially as described above, and as including IC structure 1201 (FIG. 12) following deposition and planarization of capacitor metal portion 161. As shown, the metal deposition process that forms capacitor metal portion 161 also forms shield metal portion 190. The metal deposition process that forms capacitor metal portion 161 also forms routing metal portion 163 such that shield metal portion 190 and capacitor metal portion 161 may be electrically connected (e.g., conductively) through routing metal portion 163.

FIG. 14 illustrates a mobile computing platform and a data server machine employing a memory device 1450 including BEOL shielded capacitors, for example as described elsewhere herein. The server machine 1406 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic or MCM IC-eDRAM device. The mobile computing platform 1405 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1405 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1410, and a battery 1415.

Disposed within the integrated system 1410, a substrate 1460 includes an eDRAM 1430 and processor circuitry 1440 (e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like). eDRAM 1430 includes 1C-1TFT cells, with each cell including a BEOL TFT 1431 and a BEOL shielded capacitor 1432, for example as described elsewhere herein. For monolithic embodiments, substrate 1460 is a semiconductor chip. For MCM embodiments, substrate 1460 may be any package substrate, or an interposer.

Processor circuitry 1440, or a separate RFIC chip may be further coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 1402.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. FIG. 15 is a functional block diagram of an electronic computing device 1500, in accordance with some embodiments. Computing device 1500 may be found inside platform 1405 or server machine 1406, for example. Device 1500 further includes a motherboard 1502 hosting a number of components, such as, but not limited to, a processor 1504 (e.g., an applications processor), which may further incorporate interconnect structures (e.g., line segments with compositional variation) in accordance with embodiments described herein. Processor 1504 may be physically and/or electrically coupled to motherboard 1502. In some examples, processor 1504 includes an integrated circuit die packaged within the processor 1504. In general, the term“processor” or“microprocessor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips 1506 may also be physically and/or electrically coupled to the motherboard 1502. In further implementations,

communication chips 1506 may be part of processor 1504. Depending on its applications, computing device 1500 may include other components that may or may not be physically and electrically coupled to motherboard 1502. These other components include, but are not limited to, volatile memory (e.g., MRAM 1530, DRAM 1532), non-volatile memory (e.g., ROM 1535), flash memory, a graphics processor 1522, a digital signal processor, a crypto processor, a chipset, an antenna 1525, touchscreen display 1515, touchscreen controller 1575, battery 1510, audio codec, video codec, power amplifier 1521, global positioning system (GPS) device 1540, compass 1545, accelerometer, gyroscope, audio speaker 1520, camera 1541, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips 1506 may enable wireless communications for the transfer of data to and from the computing device 1500. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 1506 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 1500 may include a plurality of communication chips 1506. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless

communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

It will be recognized that principles of the disclosure are not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below.

In first examples, an integrated circuit structure comprises a plurality of metal- insulator-metal (MIM) capacitor structures within vias. The vias are in an interlayer dielectric (ILD) material. Individual ones of the MIM capacitor structures further comprise a first metal laterally adjacent to a sidewall of a via, an insulator laterally adjacent to a sidewall of the first metal, and a first portion of a second metal laterally adjacent to a sidewall of the insulator. One or more spacers are over the ILD material. The one or more spacers comprises a dielectric material, a second portion of the second metal is over the one or more spacers. A third portion of the second metal is within a recess in the ILD material between adjacent ones of the MIM capacitor structures.

In second examples, for any of the first examples the IC structure further comprises a cap over the first metal. The cap comprises a dielectric material. The one or more spacers are laterally adjacent to a sidewall of the cap. The second portion of the second metal is over the cap. The third portion of the second metal is laterally adjacent to a sidewall of the one or more spacers, and laterally adjacent to a sidewall of the ILD material under the one or more spacers.

In third examples, for any of the first through second examples, the via has a height within the ILD material. The third portion of the second metal is adjacent to the sidewall of the ILD material over at least 50% of the height. In fourth examples, for any of the first through third examples, the one or more spacers completely enclose a circumference of the via. A lateral width of the third portion of the second metal adjacent to the sidewall of the one or more spacers is equal to a distance between the sidewall of the one or more spacers enclosing a first of the MIM capacitor structures, and a sidewall of the one or more spacers enclosing a second of the MIM capacitor structures, adjacent to the first of the MIM capacitor structures.

In fifth examples, for any of the fourth examples a lateral width of the one or more spacers is constant along a circumference of the via. A distance between sidewalls of the spacers enclosing adjacent ones of the MIM capacitor structures varies along the via circumference. The lateral width of the third portion of the second metal adjacent to the sidewall of the one or more spacers occupies the varying distance between the sidewalls.

In sixth examples, for any of the first through the fifth examples a lateral width of the third portion of the second metal adjacent to the sidewall of the one or more spacers is equal to a distance between an exterior sidewall of the first metal in adjacent ones of the MIM capacitor structures minus the lateral widths of the one or more spacers.

In seventh examples, for any of the first through the sixth examples the third portion of the second metal completely encloses the via.

In eighth examples, for any of the second through the seventh examples at least one of: the one or more spacers and the ILD material have a different composition; the cap and the ILD material have a different composition; or the one or more spacers and the cap have a different composition.

In ninth examples, for any of the first through the eighth examples the second metal is electrically coupled to a reference voltage potential, and the first metal layer of individual ones of the MIM capacitor structures is electrically coupled to a first terminal of a select transistor.

In tenth examples, for any of the first through the ninth examples the second metal is electrically coupled to a reference voltage potential and wherein the first metal layer of individual ones of the MIM capacitor structures is electrically coupled to a first terminal of a select transistor comprising an amorphous or polycrystalline semiconductor material. In eleventh examples, a computer platform comprises one or more processor; and the IC of any one of the first through the tenth examples.

In twelfth examples, an integrated circuit (IC) memory device comprises peripheral circuitry comprising a plurality of field effect transistors (FETs). Individual ones of the FETs comprise a monocrystalline semiconductor channel. The memory device comprises a memory cell array monolithically integrated with the peripheral circuitry. The array includes a plurality of metal-insulator-metal (MIM) capacitor structures coupled to a plurality of thin film transistors (TFTs). The TFTs are further electrically coupled to wordlines extending in a row direction and bitlines extending in a column direction, orthogonal to the row direction. Individual ones of the TFTs employ a poly crystalline or amorphous semiconductor channel. Individual ones of the MIM capacitor structures further comprise a first metal laterally adjacent to a sidewall of a via that is in an interlayer dielectric (ILD) material. An insulator is laterally adjacent to a sidewall of the first metal, and a first portion of a second metal is laterally adjacent to a sidewall of the insulator. The memory cell array includes one or more spacers over the ILD material. The one or more spacers comprise a dielectric material. A second portion of the second metal is over the one or more spacers. A third portion of the second metal is within a recess in the ILD material between individual ones of the MIM capacitor structures.

In thirteenth examples, for any of the twelfth examples the MIM capacitor structures have first terminals comprising the first metal. The first terminals of individual ones of the capacitor structures are electrically coupled to first semiconductor terminals of individual ones of the TFTs. The third portion of the second metal is laterally adjacent to a sidewall of the one or more spacers and laterally adjacent to a sidewall of a portion of the ILD material under the one or more spacers. The via has a height within the ILD material, and wherein the third portion of the second metal is adjacent to a sidewall of the ILD material over at least 50% of the height.

In fourteenth examples, the one or more spacers completely enclose a circumference of the via. A lateral width of the third portion of the second metal adjacent to the sidewall of the one or more spacers is equal to a distance between sidewalls of two of the one or more spacers enclosing individual ones of the MIM capacitor structures. In fifteenth examples, a method of fabricating an integrated circuit (IC) comprises depositing a backbone layer over an interlayer dielectric (ILD) material, forming a plurality of openings in the backbone layer, forming one or more spacers along an interior sidewall of individual ones of the openings, and forming vias into the ILD material not protected by either the backbone layer or the one or more spacers. The method comprises removing the backbone layer selectively to the one or more spacers, forming one or more recesses into the ILD material not protected by the one or more spacers, forming a metal-insulator-metal (MIM) capacitor structure within the vias, and forming a shield structure within the recesses.

In sixteenth examples, for any of the fifteenth examples, forming the MIM capacitor structure further comprises depositing a first metal on a sidewall of the vias. Depositing an insulator on a sidewall of the first metal, and depositing a second metal on a sidewall of the insulator.

In seventeenth examples, for any of the fifteenth through sixteenth examples forming the shield structure further comprises depositing the second metal within the recesses.

In eighteenth examples, for any of the fifteenth through the seventeenth examples, the method comprises backfilling at least a portion of the vias with a sacrificial material, planarizing the scarification material with a surface of first metal and a surface of the spacers, recessing the surface of the first metal below the surface of the spacers, and forming a cap over the recessed surface of the first metal.

In nineteenth examples, for any of the eighteenth examples the cap comprises a dielectric material, and forming the shield structure further comprises depositing the second metal over the cap, and over the one or more spacers, and within the trenches.

In twentieth examples, for any of the eighteenth examples backfilling at least a portion of the vias with sacrificial material further comprises depositing the sacrificial material over the insulator before the second metal is deposited, and forming the trenches into the ILD material concurrently removes at least some of the sacrificial material from the vias.

In twenty-first examples, for any of the fifteenth through the twentieth examples removing the mask layer selectively to the spacers exposes a portion of the ILD material between spacers enclosing adjacent ones of the vias. Forming the trenches into the ILD material comprising etching the ILD material between a first of the spacers enclosing a first of the vias, and a second of the spacers enclosing a second of the vias.

In twenty-second examples, for any of the fifteenth through the twenty-first examples forming the spacers further comprises depositing a layer of dielectric material having a different composition than the mask layer, and anistropically etching the layer of dielectric material selectively to the mask layer.

In twenty-third examples, for any of the fifteenth through the twenty-second examples at least one of: the spacers and the ILD material have a different composition; the cap and the ILD material have a different composition; or the spacers and the cap have a different composition.

In twenty-fourth examples, for any of the fifteenth through twenty-second examples the first metal layer of individual ones of the MIM capacitor structures is electrically coupled through a bottom of the vias to a first terminal of a select transistor.

In twenty-fifth examples, for any of the fifteenth through twenty-second examples the method further comprises forming a plurality of select transistors, the select transistors further comprising an amorphous or polycrystalline channel semiconductor; and

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.