TECHNICAL FIELD

The present invention generally relates to digital sampling rate conversion systems, and more specifically to devices and methods for making such systems shift-invariant and/or characterizing such systems.

BACKGROUND

Digital sampling rate conversion (SRC) systems receive sampled input signals at a given sampling rate and output the signal with a different sampling rate. The SRC system may increase (upsample) or decrease (downsample) the sampling rate of the signal.

The sampling rate conversion systems are widely used in audio or video systems for performing conversion of audio or video files from a given codec to another. SRC systems may have other applications.

Before integrating a sampling rate conversion system in a multimedia

(e.g. audio and/or video) architecture, there may be the need of characterizing the SRC system for studying its behaviour.

Different approaches to characterization and performance measurements for multirate systems exist in the prior art.

SRC may be dealt with as a specific case of a multirate system (MRS). In some prior art approaches, fractional rate sampling rate convertors (SRC) are not considered as Linear Periodically Time Varying (LPTV) systems. For an SRC, input and output periods are constrained to be different. In other approaches, assuming an explicit definition of LPTV with potentially different input and output periods, SRC is clearly considered as LPTV. LPTV systems form a wider class than SRC since filter banks belong to LPTV.

LPTV systems may be entirely described in a polyphase context with tools including: analysis network (PPAN), synthesis network (PPSN) and polyphase matrix. Typically, the following approach may be used in order to describe a LPTV system: Find a representation that embeds a Linear Time Invariant (LTI) system and characterize the LTI system with some suitable method.

Various different approaches are possible. For example, the LTI system may include a MIMO LTI system characterized by a bi-spectrum. Other approaches include a linear switched time varying (LSTV) system.

The characterizing bi-spectrum may be obtained through different means. For example via formal analysis by serial or parallel concatenation of basic building blocks (MIMO LTI system, decimator, expander, modulator), or via black box analysis with excitation of the system with a set of orthogonal test vectors.

Several techniques may be used for characterizing sampling rate conversion systems (SRC) from the outside (the SRC system being considered as a black box or a near black box (or grey) component).

The parameters characterizing the SRC system may be:

- the in-band linear characteristics of the system,

- the out-of-band characteristics of the system that generates spectrum aliases, and

- the additional background noise due to rounding errors.

The characterizing methods may be based on a distortion measurement either on a sine wave or on a sine sweep wave. The characterization methods may also be based on the reconstruction of the impulse response of the SRC system.

However, SRC systems are not shift-invariant (or time-invariant) systems. For an SRC system, the output of a delayed sequence is not necessarily the delayed version of the resulting output of the non-delayed sequence. This lack of shift-invariance generates aliasing, which penalizes the characterization methods.

Therefore, whereas the aliasing behaviour is not due to a non-linear behaviour, aliasing of SRC systems is usually studied as if it was a non-linear distortion with methods and criterion such as total distortion methods. In fact, for an SRC system, a source of non-linearity may be the rounding errors. Total distortion methods are thus unable to discriminate between aliasing and real non-linearity.

Hence, there is a need for facilitating the characterization of the SRC systems.

SUMMARY

Therefore, a first aspect of the invention relates to a method for making SRC systems shift-invariant (or time-invariant).

It is noted that embodiments of the invention may be equally applicable to any LPTV system (e.g. when P and R are not coprime), even though described below in the context to SRC systems only.

According to the first aspect, there is provided a method of converting the sampling rate of an input signal with input/output shift-invariance using a Linear Periodically Time Varying, LPTV, system.

The method comprises generating a set of polyphase components of the input signal.

The LPTV system being a digital Sampling Rate Conversion, SRC, system and having a fractional ratio — , with R and P being co-primes, the method further comprises selecting three integer numbers Q, M and q that satisfy the following equations:

M=RQ,

q=PQ, and

MP=qR,

and the generation of each polyphase component of the set of polyphase components comprises

- time shifting the input signal a number of times comprised between 0 and MP; and,

- M-fold decimating the time shifted input signals

The method further comprises:

- feeding the generated set of polyphase components to the SRC system; and, - generating an output signal corresponding to the input signal with converted sampling rate, by performing interleaving, shifting and addition on signals output by the SRC system corresponding to the generated set of polyphase components processed by said SRC system.

Once the SRC system is made shift-invariant (or time-invariant) LTI

(Linear Time Invariant) characterization methods can be applied and true non- linearity of the SRC system can be studied separately.

A second aspect of the invention relates to a method of characterizing a Linear Periodically Time Varying, LPTV system being a Sampling Rate Conversion, SRC system. The method comprises:

- inputting at least one input signal being one of the group consisting of: an impulse and a test sequence;

- implementing a method according to the first aspect with the input signal; and,

- characterizing the SRC system through the output signal.

In a variant, the second aspect relates to a method of characterizing a

Linear Periodically Time Varying, LPTV, system comprising:

- inputting at least one input signal being one of the group consisting of: a sine- sweep signal, a sine signal, multiple sine signals, a multi-sine signal, multiple multi-sine signals, a maximum length sequence, or an all pass filtered impulse signal;

- implementing a method according to the first aspect, with the input signal; and,

- characterizing the LPTV system through the output signal.

Embodiments of the invention are recited in the dependent claims attached hereto.

For example, the method may be performed in real time. In such an embodiment, different instantiations of the SRC system may be used for generating in parallel the polyphase components.

In other embodiments, the polyphase components may be generated by a same instantiation of the SRC system.

The output signal may be generated by an overlapping-add operation.

Once the method implemented, SRC systems behave as linear and shift invariant (LSI) systems. Hence, the SRC systems may be modelled as discrete filters operating in the oversampling domain. According to some embodiments, the alias components are pushed out of the bandwidth of the SRC system, which facilitates the characterization of the SRC system.

Thus, methods for characterizing shift-invariant systems can be applied in the oversampled domain.

For example, the impulse response characterization method or the transfer function characterization method may be used.

Once the SRC system is made shift-invariant, any remaining distortion or background noise in the SRC system may be associated to internal rounding errors caused by the arithmetic of the SRC system.

Therefore, any distortion method identifying these non-linearities can be used in the oversampled domain for characterizing those rounding errors, and then the SRC system.

For example, the Harmonic distortion method, or the Exponential Sine-Sweep may be used.

A third aspect of the present invention relates to a computer program product comprising one or more stored sequences of instructions that are accessible to a processor and which, when executed by the processor, cause the processor to carry out the steps of the method of the first and/or the second aspect of the present invention.

A fourth aspect of the present invention relates to a system for converting the sampling rate of an input signal with input/output shift-invariance comprising:

- a Linear Periodically Time Varying, LPTV, system being a Sampling Rate

Conversion, SRC system having a fractional ratio — , with R and P being co- primes;

- a first input port adapted to receive the input signal;

- a first output port adapted to output polyphase components of the input signal to the SRC system,

- a second input port adapted to receive signals outputted by the SRC system corresponding to the polyphase components processed by said SRC system,

- a processing unit being adapted to generate the polyphase components and to select three integer numbers Q, M and q that satisfy the following equations: M=RQ,

q=PQ, and

MP=qR,

said processing unit comprising:

- a time shifting unit adapted to time shift the input signal a number of times comprised between 0 and MP, and

- an M-fold decimator adapted to decimate the time shifted input signals, and being further adapted to perform interleaving, shifting and addition on the signals outputted by the SRC system for generating an output signal, and

- a second output port adapted to output the generated output signal.

A fifth aspect of the present invention relates to a system configured to characterize a sampling rate conversion system comprising:

- a system according to the fourth aspect, and

- a characterization unit adapted to perform a method according to the second aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements and in which:

- Figure 1 is a schematic illustration of an SRC system;

- Figures 2a, 2b, 2c are flowcharts illustrating steps of methods according to embodiments of the invention;

- Figures 3a and 3b are a schematic illustrations of multi-rate frameworks according to embodiments of the invention;

- Figure 4 is a schematic illustration of a system according to embodiments of the invention;

- Figures 5 and 6 illustrate the evaluation of the transfer function of an SRC system according to embodiments of the invention; and - Figures 7 and 8 illustrate the un-aliasing effect of embodiments of the invention. DESCRIPTION OF EMBODIMENTS

In the following, we consider a digital sampling rate conversion (SRC) system having a fractional ratio R/P (R and P being co-primes).

An SRC system 100 may be represented as the association of an R-fold expander 101 , followed by a low-pass filter 102, and followed by a P-fold decimator 103, as illustrated in Figure 1.

In some embodiments the system 100 may be seen as a canonical representation for a resampler, 101 combined with 102 as an integer rate upsampler and 102 combined with 103 as an integer rate downsampler.

This representation always exists and is unique. Therefore, it is a canonical representation. The canonical representation of an SRC may be different from the actual implementation. In implementations that include multistage operations with possible interpolation algorithms, the canonical representation of the SRC system may be either unknown or difficult to retrieve.

The parameters characterizing the SRC algorithms used in SRC systems may be defined by the properties of the low pass filter H(z) as it will be apparent to the person with ordinary skill in the art.

Thus, the SRC system may be characterized, for example, by determining the z-transform of the impulse response H(z) of the low-pass filter, or its transfer v

ιπ—

function ^{H (} v designating the reduced pulsation, and R the expansion ratio from the SRC system.

According to some embodiments, as illustrated by Figure 2a, an input discretized signal, the sampling rate of which is to be converted by the SRC system, is received in a first step S201 . Then, during step S202, a set of polyphase components (as further described hereafter) is generated, based on the input signal.

For example, as illustrated by Figure 2b, step S202 may comprise a step S203 of time shifting the input signal k times, with k being an integer inclusively comprised between 0 and MP-1 (M verifying M=RQ, q=PQ, and MP=qR, q and Q being integer numbers, R and P being co-prime integers), and the step S204 of M-fold decimating the time shifted signals. After step S202, a step S205 of feeding the SRC system with the polyphase components is performed.

The polyphase components may be fed to a same instantiation of the SRC system. However, for example for real time applications, wherein the output samples of the different instantiations of the SRC systems produced at the same time are grouped within one frame, the SRC system may be instantiated a number of times equal to the number of polyphase components. Then, the processing of the polyphase components by the instantiations of the SRC system may be performed at the same time (in parallel). Other variants of the number of instantiations and feeding of polyphase components may also be applicable.

Then, after step S205, a step S206 of generating an output signal is performed. The output signal is generated based on the output of the SRC system (or the outputs of the different instantiations of the SRC system). The output signal is generated by interleaving, shifting and adding the signals output by the SRC system (or the outputs of the different instantiations of the SRC system). The output signal may also be generated by an overlapping add operation on the outputs of the SRC system (for example in case of a real time application).

For example, as illustrated by Figure 2c, step S206 may comprise initializing the generation of the output signal S207, by receiving the signal output by the SRC corresponding to the polyphase component which has not been time shifted (corresponding to k=0). Then, in step S208, the received signal is expanded at a rate of PQ, and the expanded signal is then time shifted in step S209. Then, the process continues with step S210 by receiving the output signal of the SRC system that has been time shifted k+1 times. This output signal is expanded at a rate of PQ during step S21 1 , and the resulting signal is added, in step S212, to a previous addition of the processed signals (corresponding to the polyphase components time shifted a number of times 0, 1 , k). Then in step S213, it is verified whether all the output signals from the SRC system have been processed. If P-1 output signal have been processed, then the generation of the output signal is terminated in step S214 and the output signal corresponds to the sum calculated in the last iteration of step S21 1 . In the other case, the sum calculated in the last iteration of step S212 is time shifted in step S215 and the process goes back to step S210. The above described embodiment is also illustrated by the multi-rate frameworks of Figures 3a and 3b.

Figure 3a shows a number PQR of parallel processing lines each comprising a QR-fold decimator, the SRC system with a rate of R/P and a PQ-fold expander. The input signal is fed to a first processing line and to a delay z ^"1 that outputs the delayed signal to another processing line and to another delay, and so on until the last processing line receives the input signal delayed PQR times. The first processing line outputs a signal to a delay z ^"1 that feds the delayed signal to an adder that sums the delayed signal and the output of the second processing line and so on. The combination of the delays and the adders performs the operation of overlap add.

Figure 3b shows an alternative framework using anti-causal advances z. In this framework, the input signal b is fed to the last processing line and the delays z ^"1 of the left side of the framework are replaced by advances z.

A system according to some embodiments is illustrated by Figure 4.

The system comprises an input port 401 for receiving a signal at a rate M times the operating input rate of the SRC system 402. The input port 401 may also receive a signal used for characterizing the SRC system 402.

The system further comprises a processing unit 403 for generating the polyphase components. These polyphase components may be fed to the SRC system 403 through an output port 404 that may be coupled to an input port 405 of the SRC system.

The system further comprises an input port 406 for receiving signals output by the SRC system through its output port 41 2 corresponding to the processed polyphase components. These processed polyphase components may be used by the processing unit 403 for generating and outputting the output signal through an output port 407.

The output port 407 receives a signal at a rate q time the operating output rate of the SRC system. The feeding rate of 401 is identical to the filling rate of 407.

The processing unit may comprise a decimator 408, an expander 409, and a time shifting unit 41 0. According to some embodiments, the system may comprise a characterization unit 41 1 for characterizing the SRC system.

Also, the system according to embodiments may comprise a memory unit 413 for storing data for the implementation of a method according to embodiments of the invention, or storing a computer program according to embodiments of the invention.

In the following, the method for making the SRC system shift-invariant is further explicated.

Making the SRC system shift-invariant

In the following, it is shown how a set of system responses organized as a sum of interleaved and shifted signal is linear and time-invariant when this set forms a set of regularly delayed signals from 0 to MP-1 samples.

Under those conditions, the z-transforms S(z) of the interleave-shift-added (ISA) system responses follow an expression which allows a characterization of the SRC system for both in-band and out-of-band domains (B(z) being the z- transform from an interleaved test sequence):

S(z) = H {zQ) x B(z)

Example 1: Upsampler

Let's consider the problem of characterizing an upsampler with a rate of R = 3. The upsampler may be characterized by its canonical representation through a

(h (z^) )

low pass filter H(z). The R-polyphase decomposition ^ " ) )ie [o,R) ₀ f |_|( _z ) j _s given as:

R- l

H(z) = z ^~ %(z ^R )

=0

For the sake of readability, in the following, a sequence (s„)„ _eS may be assimilated to its z-transform S(z). Now, we consider a set of test vectors M , for instance slightly delayed versions of a band-limited unit impulse or, said differently, an approximation of the k_

shifted unit z ^M (this being only a notation for a sequence describing a fractional k_

delay of the shifted unit impulse, here does not equal z ).

K (z)

The individual vectors ^ are obtained as the M-polyphase decomposition of B(z):

For the matter of this example, consider M = 24, which is not too large but still shares a common denominator with most usual resampling ratios (apart ratios translating sampling rates from the 44.1 kHz domain to sampling rates simple multiple of 8kHz).

Let's start with the processing (i.e. here, the up-sampling) of each test

(z) ¾(z)

vectors M , resulting into the vectors M . The label kR/M is chosen in order

¾ (Z) kR to remind that if everything was ideal, ^M would match the fractional delay z ^M .

R- l

8 ψ ( ^ζ ) = Γ ζ- (ζ^ (ζ ) = H(z) ^■ b^ (z ^R )

'=°

In this case, we have M/R = Q = 8 and therefore the 8 first processed vectors form a polyphase decomposition of the unit impulse: So/s(z), Si _/8 (z),- ^{■ ■} , s ₇ /s(z).

Therefore, let's consider S ₀ (z) obtained as the result of interleaving those 8 vectors: fe=0

vfe=0

Now, S ₀ (z) is separable; define as the second term of this product:

Then, we have:

One may note that the 8 following processed vectors form another polyphase decomposition of the unit impulse: s ₈ /8(z), s _9/8 (z), ^{■ ■ ■} , Si _5/8 (z). We can consider 5 _] (ζ) obtained as the result of interleaving those 8 one-sample shifted vectors,

. ( ^"ls fc/8( ² )) _fc€[ 8,16).

S _l (z) = : ^h Z ^¾ .5' (fe ₊ M).R. (Z ^S ) — Z ^k Skh

k^O ' k 8

Note also that the 8 last processed vectors form again another decomposition of the unit impulse: Si ₆ /8(z), Si7/s(z), ^{■ ■ ■} , s ₂ 3/s(z). S ₂ (z) is obtained as the result of interleaving those 8 two-sample shifted vectors, i.e. ^f c<≡[i 4).

7 23

S ₂ ( ^K z) ' = Z j z- ^k z- ^w s - ₍ — _k - _2jM — ₎ -— _R (z ⁸ ) > = / j z- ^k s - _kR - _f (z ^H ) ¹

k=0 " Α:=16

Finally we have S(z), the z-transform from the sequence obtained as the addition from the three previous sequences: S(z) =∑S _l (z) = H(zQ)∑ ft {z)

1=0 1=0

We can recognize in ^■ * v~ ⁾ the z-transform B(z) (cf. Equation 1 ).

Therefore, we have generated a sequence as the interleave-shift-add (ISA)

¾ (z)

operation from the processed test vectors M , which z-transform, S(z), is not only separable from H(z), but can also be divided by B(z) (i.e. the z-transform from the interleaved test sequences):

Example 2: Downsampler

We consider the case of a simple downsampler of rate 1/P.

bAz)

Test vectors ^ are obtained as the M-polyphase decomposition of B(z) (cf. example 1 , with for instance M = 24):

M-l

z ^{~ k} h^ (z ^M )

k=0 Consider also the continuation of the test vectors M for k > M: fk e [0. ), VI e Z 5, b _k + i M

_____ ( Vz ^M ) / - z ^l b "M (z ^M ) bAz) Sj_ (z)

The down-sampling of any test vector M results into the vector MP with ^ω ρ being a non-obvious root from X ^p - 1 . Now, consider the z-transform S(z) of the sequence obtained by interleaving MP

^(z)

consecutive sequences derived from MP , for instance starting from k = 0:

MP-l

MP

k=0

MP-l P-l

,M-

P ∑ ∑ H ^J P

k=0 τη—ΰ

P-l MP-l

P P / * ^{v r} ' / J

0 k = 0

Consider the second part from this expression:

MP-l k=0 k=0 1=0

M-l P-l k=0 1=0

/,·.=ο /=0

Note that ^{A' ' 1} ( ^{~~ x} )∑ ( ^/ . Therefore, if ^ω Ρ ≠ ', then /=n ^ω Ρ ^{— υ} . Said differently and using the Kronecker symbol :

Now, let's return to the original evaluation: P- l M- 1

S(z) = ∑ Η(ωψ ^ζΜ )∑ ^ζ - (ωψ ^ζΜ )∑δ η-, Ρ

= H(z ^M )B(z)

This concludes the evaluation of S(z) in the simple down-sampling case:

S(z) = H(z ^M ) x B{z) (4)

This equation is similar to Eq.(3). This proves once again that ' can be estimated and that both in-band and out-of-band characteristics can be safely recovered.

General Case We consider the characterization of a resampler with a fractional ratio R/P, R and P being co-primes. Following the upsampler example, we assume that this resampler is characterized by the unknown filter H(z) in its canonical representation.

An integer M is selected so that Q - M/R is an integer number. An integer q is defined as q = MP/R. The following relationships recap the properties between P, R, M and q:

M = RQ, q = PQ, MP = qR.

K (z)

Finally, we consider the set of test vectors « obtained as the M-polyphase decomposition of B(z) (cf. example 1 ):

O

Define also the composite root " ^m -" as: VTO€ [0, P), V e [0, ), , m ,n

Ω

, ,mR+nP

^PQR

For further calculus, define also A ^m (z) (cf. the upsampler example) and B _m (z) as:

Q-i

VZ G [0, P), β (ζ) = z- ^k b _k+lQ {ω

fc-=0

PR-l

Vm e fO,P),

1=0

Pfi-l Q-l

1

k + lQ

1=0 k=Q

k + IQ with k ine[0,Q) and I ine[0, PR) covers the entire range [0, qR). Therefore, the previous sum can be rewritten as:

qR— 1

Vm <G ΓΟ,Ρ), UJ p

,Rm

" <2

For the second evaluation, we have and therefore:

fe+iQ M-l n=0

Now, let evaluate ^ ^and finally B _m (z): O-i

Λ1-·.

k=o

JQ Q-l M-l

M

k=0 n=Q

₁ Pfi-1

1=0

PQfl-lM-l

^V fc=0 n=0

The resampling of any test vector M ^Z by the fractional ratio R/P results into the vector ^{MP z q} (cf. Appendix).

P-l

TO ,Ρ"

Sfc (2 ^P ) =— Ηίω ^' ρζ) ^■ b _k (up

m=U Consider the ISA sequence, S(z), derived from qR consecutive sequences ^q e.g. with k in [0, qR). This ISA sequence results from the sum of R shifted interleaved sequences, ^'v- . Each of those sequences, H^, is the result from interleaving q consecutive sequences ^q , e.g. for k in [Iq, (1+1 )q) (cf. the upsampler example for another slightly different -but equivalent- practical description for the ISA procedure). This process is described in Figure 3b. R-l

S(z) = ∑^ ^" ¾W

1=0

R-l q-l

∑ -''∑ -*._±_: ( ^. )

fc=0 m=0 m=0 fc=0

P-l m=0

£»(O _m. „z)

Let evaluate this expression in term of

P-lqR-lM-l

^{S{Z) =} PGR∑ ∑ ∑ ii(^ )n ,„B(0,„ ^, ,, ₂ )

^ ^' m=0 fc=0 n=0

Since P and R are co-primes, mR + nP mod (PQR) covers exactly the range [0, PQR) when m is in [0, P) and n in [0,RQ). Therefore, the double sum in m and n can be replaced by a simple sum in i, with m = ixR _^ R eing the multiplicative inverse from R in the ring

JPQR

Since is a root of the unity, we have: PQR- 1

k=0 r

This concludes the evaluation of S(z) and generalizes both Eq.(4) and Eq.(3):

S(z) = H(z ^Q ) x B(z) (5)

The transfer function ⁷ from the resampler of ratio R/P can be estimated and both in-band and out-of-band characteristics can be recovered.

Figures 7 and 8 illustrate an effect of the method that makes the SRC system shift invariant, which is the spectral un-aliasing. Figure 7 shows the spectrum of an output signal of a conventional SRC system (the ordinate show the gain in dB, and the abscissa show the normalized pulsation). All the components of the spectrum are in the frequency band between 0 and 1 . The spectrum comprises the main spectrum of the output signal A, and also aliased components B and C. Figure 8 shows the spectrum of an output signal of the same SRC system made shift-invariant according to an embodiment. In his spectrum, only the main spectrum A is in the frequency band between 0 and 1 . The aliased components B and C have been rejected out of the band.

APPENDIX

The object of this appendix is to evaluate the polyphase expression of a re- sampled signal.

Consider the input sequence which z-transform is b(z). Consider a fractional resampler x R/P the canonical representation of which is based on the low pass filter H(z). Let evaluate the z-transform s(z) of the re-sampled signal. In order to do so, consider first the z-transform σ(ζ) resulting from the R-expansion:

a(z) = H (z) - b{z ^R )

The z-transform s(z) is obtained from σ( z ) after a P-fold decimation; when we consider a 0 offset for this decimation, we obtain (with ω _ρ being a root of X ^p - 1 ):

Altogether, we obtain: p Z

The characterization of an SRC system

In the previous examples, the transfer function for a resampler with a fractional ratio R/P was established in Eq.(5), for instance, evaluated in the oversampled normalized domain:

Vv e [0, A/), S(e ^j TT ) = if( _e -' ¾f ) _x 5( _e ^J' ir )

Note that *-> l ^e J includes M/R duplications of ^{y /} ( ^{e R} J. One possible way to recover H(e^ « ) f _rom S(e ^J M ) j _s therefore to reweight appropriately each duplicate:

with, for instance the following wei

It is even possible to take into account spectrum duplicates corresponding to negative frequencies: B{e>

with, in that case, the weights updated accordingly:

k/ ^M was previously presented as an approximation from a shifted unit impulse. However, this assumption is not needed in order to obtain Eq.(3). Indeed, for the same reasons than for regular filter transfer function characterization, a pseudo- noise excitation vector can be preferred to the impulse-response method, in our case, a specifically designed set of test vectors can also be preferred to a band- limit impulse response. The recover formula in Eq.(6) indicates that it is even not necessary for ^( ^{e' M} ) to be exactly non-zero since the duplications for H ( e^ produce redundancy and therefore a tolerance to zeros.

An additional possibility for recovering H(z) and to increase tolerance to zeros (and incidentally tolerance to floating-point rounding errors) is to consider multiple answers - i to different sets of test vectors instead of S(z) alone. In such case, the recovery formula Eq.(6) is generalized by:

H( e 3 7) with, once again, the generalized weighting

./z"(y±2Zfi)

(if > (e ^M ))

Said differently, it is enough for the aliased transfer functions " ^? to cover the range [0,R) in the oversampled normalized spectral domain in order to recover safely the transfer function H(e ^3' « )

Figures 5 and 6 illustrate how the transfer function of two different upsampler systems (plain and dotted curves) for rate x3 can be evaluated for respectively the in-band (Figure 5) and the out-of-band (Figure 6) domain. One can see that in the in-band domain, the systems behave linearly. The spectral aliases have been pushed in the out-of-band. Those estimations were obtained with the help of complementary sets of test vectors, B ^{(1 )} (z) and B ⁽²⁾ (z). The first set, is obtained with a low-order low-pass filter. The second set of test vectors ^ is derived from by a modulation at the Nyquist frequency (i.e. a multiplication by the sequence 1 ,-1 ,1 ,-1 ,1 . . . ). Instead of recovering the transfer function H (e ³ « ^ † _ne multi-rate framework from Figure 3 can be used in order to recover the impulse response h _n instead. The impulse response h _n is directly available as y _n if an impulse is fed as x _n and Q

A

is set to 1. When x _n is set to an impulse ⁿ , only remains ^ ^{_ z} for m in [0, P); any other contribution being pure zero:

P- l

H(Z ) = Z ^{~ m R} S rn R (z ^P ) _{n P+mR} = S rn R (u) m=0

In the impulse method, the amount of processed vector needed is reduced: P processed vectors for the impulse method instead of at least PQR for other methods such as the transfer function method. However, it is possible that the redundancies aspects in the transfer function method guaranty a better robustness against quantization noises.

Those simple examples demonstrate the different possibilities available for estimating an upsampler transfer function and to reveal the upsampler design characteristics for both in-band and out-of-band spectral domains.

Harmonic Distortion

The Total Harmonic Distortion (THD) method is a power comparison between the original signal (sine wave) and the signal obtained by extracting the harmonic partials (comb filter) generated by the system on the original sine wave.

The Total Distortion (THD+Noise) method is a power comparison between the original signal (sine wave) and the signal obtained by removing the sine wave component from the distorted tone.

The test input signal b is a sine wave which period in the oversampled domain is Mp samples.

Then, the above discussed method making the SRC system shift- invariant is performed in order to produce the output signal s.

The width of the support of s is denoted Igt.

The complex vector * of size Igt is Discrete Fourier Transform of the output signal s. k— —

The element indexed by ^2Rp in the vector ^Sk corresponds to the source sine wave. The harmonic distortion of the source sine can be found in the vector * for every indexes multiple of kO, i.e. for k=jk0, with j from 0 to pR-1 .

Since the analysed system is made shift-invariant by the present method, the only source of harmonic non-linearities originates from rounding error due to the floating-point or fixed-point arithmetic used internally by the device.

Exponential Sine-Sweep

The Sine Sweep method consists in the generation of a sine sweep as the input signal and the examination in a time-frequency domain (e.g. a spectrogram) of the SRC processing. This examination reveals separable alias trajectories for each aliased components; it reveals also the characteristics from the in-band linear response which is roughly available as the time envelop from the time response.

The Exponential Sine-Sweep consists in the generating an exponential sine-sweep in the oversampled domain and feeding it to the LSI system. The output reveals separately the linear characteristics, the stop-band characteristics and the rounding-error characteristics.

The Exponential Sine Sweep (ESS) method, aims at characterizing simultaneously the linear and non-linear behaviour of a device (e.g. a transducer) provided that this device follows a model restricted to a certain subclass of Volterra Kernels.

When the ESS test vector is fed into a non-linear device, each distorted harmonic component appears as an anti-causal echo. Deconvolution separates each echo and allows objective measurement.

The sine wave used in the Harmonic Distortion method is replaced by an Exponential Sine-Sweep. Then, the Exponential Sine-Sweep (ESS) method is applied in the oversampled domain in order to characterize the shift-invariant system.

The ESS method applied to the SRC system enables to access to the linear characteristics of the SRC (i.e. the in-band and out-of-band characteristics from the core low-pass filter H) as well as the harmonic distortion characteristics of the algorithms (originating from rounding errors in internal arithmetics).

The Silence Sweep method allows the measure of the total distortion instead of the harmonic distortion. The idea relies on replacing the original sine sweep by a sine sweep subtracted from a pseudo-noise.

Embodiments of the present invention can be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which - when loaded in an information processing system - is able to carry out these methods. Computer program means or computer program in the present context mean any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after a conversion to another language. Such a computer program can be designed based on the flowchart of Figures 2a, 2b, 2c, Figure 3, and the present description. The computer program can be stored on a computer or machine readable medium allowing data, instructions, messages or message packets, and other machine readable information to be read from the medium. The computer or machine readable medium may include non-volatile memory, such as ROM, Flash memory, Disk drive memory, CD-ROM, and other permanent storage. Additionally, a computer or machine readable medium may include, for example, volatile storage such as RAM, buffers, cache memory, and network circuits. Furthermore, the computer or machine readable medium may comprise computer or machine readable information in a transitory state medium such as a network link and/or a network interface, including a wired network or a wireless network, that allow a device to read such computer or machine readable information.

Embodiments of the invention can be embedded in hardware circuits. For example, the circuits are implemented by the preparation of ASICs, FPGAs, microcontrollers or discrete logic elements by interconnecting an appropriate network of conventional component circuits. The circuit may also comprise memory elements such as ROMs, RAMs, EPROMs, EEPROMs, Flash memory, magnetic or optical cards, or any type of media suitable for storing electronic information.

Expressions such as "comprise", "include", "incorporate", "contain", "is" and "have" are to be construed in a non-exclusive manner when interpreting the description and its associated claims, namely construed to allow for other items or components which are not explicitly defined also to be present. Reference to the singular is also to be construed in be a reference to the plural and vice versa.

While there has been illustrated and described what are presently considered to be the preferred embodiments of the present invention, it will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from the true scope of the present invention. Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Furthermore, an embodiment of the present invention may not include all of the features described above. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims.

A person skilled in the art will readily appreciate that various parameters disclosed in the description may be modified and that various embodiments disclosed may be combined without departing from the scope of the invention.