Title:
SHIFT REGISTER CIRCUIT AND DISPLAY DEVICE PROVIDED WITH SAME
Document Type and Number:
WIPO Patent Application WO/2016/136528
Kind Code:
A1
Abstract:
The present invention realizes a shift register circuit that enables a display device to achieve higher definition with as small a number of elements as possible without causing a malfunction. A unit circuit is provided with: a thin film transistor (M5) that functions as an output control transistor; a thin film transistor (M1) for precharging an internal node (VC) on the basis of an on-level signal outputted from an output terminal (48) in a previous stage; two thin film transistors (M2, M3) arranged in series between the output terminal (48) in the previous stage and the internal node (VC) in this stage; a thin film transistor (M4) arranged between the internal node and the output terminal (48); and a thin film transistor (M6) for pulling down the output terminal (48). The thin film transistors (M2, M3) are in the ON state only for a quarter of a period of a clock cycle in a part of a period during which the output terminal (48) in the previous stage is being pulled down.
Inventors:
OGAWA YASUYUKI
YAMAMOTO KAORU
YAMAMOTO KAORU
Application Number:
PCT/JP2016/054374
Publication Date:
September 01, 2016
Filing Date:
February 16, 2016
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
G11C19/28; G09G3/20; G09G3/36
Domestic Patent References:
| WO2014054518A1 | 2014-04-10 | |||
| WO2014208123A1 | 2014-12-31 | |||
| WO2016002644A1 | 2016-01-07 |
Foreign References:
| US20140043304A1 | 2014-02-13 |
Attorney, Agent or Firm:
SHIMADA, AKIHIRO (JP)
Akihiro Shimada (JP)
Akihiro Shimada (JP)
Download PDF: