SHIFT-REGISTER CIRCUIT, GATE-DRIVING CIRCUIT, AND ARRAY SUBSTRATE OF A DISPLAY PANEL

Title:

SHIFT-REGISTER CIRCUIT, GATE-DRIVING CIRCUIT, AND ARRAY SUBSTRATE OF A DISPLAY PANEL

Document Type and Number:

WIPO Patent Application WO/2019/029071

Kind Code:

A1

Abstract:

A shift-register circuit configured as one of a plurality of shift-register units cascaded in series. The shift-register circuit includes a pull-up sub-circuit (2) coupled to a pull-up node (PU), a first clock port (CLK), and an output port (OUTPUT). The pull-up sub-circuit (2) is configured to pass a first clock signal from the first clock port (CLK) to the output port (OUTPUT) when the pull-up node (PU) is set to a turn-on voltage. Additionally, the shift-register circuit includes a chamfering sub-circuit (1) coupled to the pull-up node (PU), the first clock port (CLK), a chamfering clock port (CLKB), and the output port(OUTPUT). The chamfering sub-circuit (1) is configured to pass a chamfering clock signal from the chamfering clock port (CLKB) to the output port (OUTPUT). The chamfering clock signal (CLKB) is at the turn-on voltage simultaneously with the first clock signal and becomes a turn-off voltage slightly earlier in time than the first clock signal.

Inventors:

LIANG XUEBO (CN)
TANG XIUZHU (CN)
QIAN QIAN (CN)
CHEN SHUAI (CN)
ZHAO JINGPENG (CN)
TANG TAOLIANG (CN)
DONG XING (CN)
XIONG LIJUN (CN)
TIAN ZHENGUO (CN)
HU SHUANG (CN)

Application Number:

PCT/CN2017/115598

Publication Date:

February 14, 2019

Filing Date:

December 12, 2017

Export Citation:

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Assignee:

BOE TECHNOLOGY GROUP CO LTD (CN)
CHONGQING BOE OPTOELECTRONICS TECH CO LTD (CN)

International Classes:

G09G3/20

Foreign References:

CN106057116A	2016-10-26
CN103680427A	2014-03-26
CN106098101A	2016-11-09
CN103366822A	2013-10-23
CN104123918A	2014-10-29
CN101644867A	2010-02-10
US20050104836A1	2005-05-19

Other References: