Title:
SHIFT REGISTER AND DISPLAY DEVICE PROVIDED WITH SAME
Document Type and Number:
WIPO Patent Application WO/2019/017264
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a shift register that is capable of suppressing occurrence of an erroneous operation caused by off-leakage at a thin-film transistor and stopping a shifting operation to be performed at an arbitrarily defined stage. A plurality of clock signals are provided to the shift register so as to generate a shifting operation stop period where the shifting operation is stopped. A unit circuit constituting each stage of the shift register is provided with a thin-film transistor (output control transistor)(T9) that controls outputting of an output signal (Q) which becomes a scanning signal, a first node (output control node)(NA) that is connected to the thin-film transistor (T9), and a first charge supply circuit (410) that supplies charges to the first node (NA) during the shifting operation stop period when being at an intermediate stage where the shifting operation has stopped.
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Inventors:
GYOUTEN SEIJIROU
TSUJINO SACHIO
HORIUCHI SATOSHI
ASAI YOSHIHIRO
OGASAWARA ISAO
TSUJINO SACHIO
HORIUCHI SATOSHI
ASAI YOSHIHIRO
OGASAWARA ISAO
Application Number:
PCT/JP2018/026267
Publication Date:
January 24, 2019
Filing Date:
July 12, 2018
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
G09G3/36; G09G3/20; G11C19/28
Foreign References:
| US20160034097A1 | 2016-02-04 | |||
| US20180033391A1 | 2018-02-01 | |||
| US20170123539A1 | 2017-05-04 | |||
| US20160274713A1 | 2016-09-22 | |||
| JP2014182203A | 2014-09-29 |
Attorney, Agent or Firm:
SHIMADA, Akihiro et al. (JP)
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