Title:
SHIFT REGISTER, SCANNING SIGNAL LINE DRIVE CIRCUIT, AND DISPLAY DEVICE
Document Type and Number:
WIPO Patent Application WO/2011/114569
Kind Code:
A1
Abstract:
In a monolithic gate driver, power consumption is reduced in comparison to that achieved in the past, without lowering the voltage applied to a gate bus line. A bistable circuit is provided with: an output terminal (51) which outputs a state signal (Q); an output terminal (52) which outputs a different-level control signal (Z); a first node which has a potential that is controlled in accordance with a set signal (S) and a clear signal (CLR); a thin-film transistor (T1) which passes the potential of a second clock (CKB) to the output terminal (51) when the potential of the first node is at a high level; a thin-film transistor (T2) which passes the potential of a first clock (CKA) to the output terminal (52) when the potential of the first node is at a high level; and a thin-film transistor (T4) which changes the potential of the different-level control signal (Z) to a low level in accordance with a reset signal (R). The first clock (CKA) is produced by a power source of a different system from the second clock (CKB) and has a lower amplitude than the second clock (CKB).
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Inventors:
FUKAYA, Tetsuo (())
深谷 哲生 (())
YONEMARU, Masashi (())
米丸 政司 (())
深谷 哲生 (())
YONEMARU, Masashi (())
米丸 政司 (())
Application Number:
JP2010/069321
Publication Date:
September 22, 2011
Filing Date:
October 29, 2010
Export Citation:
Assignee:
SHARP KABUSHIKI KAISHA (22-22, Nagaike-cho Abeno-ku, Osaka-sh, Osaka 22, 〒5458522, JP)
シャープ株式会社 (〒22 大阪府大阪市阿倍野区長池町２２番２２号 Osaka, 〒5458522, JP)
FUKAYA, Tetsuo (())
深谷 哲生 (())
YONEMARU, Masashi (())
シャープ株式会社 (〒22 大阪府大阪市阿倍野区長池町２２番２２号 Osaka, 〒5458522, JP)
FUKAYA, Tetsuo (())
深谷 哲生 (())
YONEMARU, Masashi (())
International Classes:
G11C19/28; G09G3/20; G09G3/36; G11C19/00
Attorney, Agent or Firm:
SHIMADA, Akihiro (Shimada Patent Firm, Manseian Building 1-10-3, Yagi-cho, Kashihara-sh, Nara 78, 〒6340078, JP)
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Claims: